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公开(公告)号：US20060213270A1
公开(公告)日：2006-09-28
申请号：US11370764
申请日：2006-03-08
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01P15/125
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.
摘要翻译： 用于感测电容器的电容的单端电容器接口电路包括具有输入共模电压的差分积分放大器和电压基本上等于输入共模电压的两个求和节点，用于将电容器充电到第一 电压电平在第一阶段中，在第二阶段将电容器连接到差分放大器的求和节点之一，以提供基本上代表第一电压电平和输入共模电压之间的差的第一输出变化，以及 也代表电容器; 在第三相中将电容器充电到第二电压电平，并且在第四相中将电容器连接到差分放大器的另一个求和节点，以提供基本上代表第二电压电平与第二电压电平之间的差的第二输出变化 输入共模电压，也代表电容; 组合的第一和第二输出变化表示电容器的电容基本上独立于输入共模电压。
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公开(公告)号：US20050156769A1
公开(公告)日：2005-07-21
申请号：US11005126
申请日：2004-12-06
申请人： John O'Dowd , Thomas Meany , Tomas Tansley
发明人： John O'Dowd , Thomas Meany , Tomas Tansley
摘要： A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.
摘要翻译： 一种减少的斩波速率模数转换器技术，包括选择性地将输入采样加权到数字滤波器，将输入误差的极性交替地反转为正和负误差分量; 以及在数字滤波器的多个时间响应间隔中产生正和负误差分量，其中正误差分量和负误差分量的权重之和基本相等。
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13.发明授权公开(公告)号：US08640868B2
公开(公告)日：2014-02-04
申请号：US13350587
申请日：2012-01-13
申请人： John O'Dowd , Canay Tulunay Riordan
发明人： John O'Dowd , Canay Tulunay Riordan
CPC分类号： G06F1/1628 , G06F1/1632 , H04M1/185
摘要： A case assembly for a portable device is provided that has a first sleeve member, a second sleeve member and a customized plate member. The first sleeve member is mated with the second sleeve member to encase the portable device. The customized plate member is configured and arranged to connect with the first sleeve member and the second sleeve member.
摘要翻译： 提供了一种用于便携式设备的壳体组件，其具有第一套筒构件，第二套筒构件和定制板构件。 第一套筒构件与第二套筒构件配合以封装便携式装置。 定制的板构件被构造和布置成与第一套筒构件和第二套筒构件连接。
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公开(公告)号：US07304483B2
公开(公告)日：2007-12-04
申请号：US11821746
申请日：2007-06-25
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.
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公开(公告)号：US20070247171A1
公开(公告)日：2007-10-25
申请号：US11821746
申请日：2007-06-25
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01R27/26
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.
摘要翻译： 用于感测第一和第二电容器的电容的差分电容器一端电容器接口电路包括具有第一和第二求和节点和输入共模电压的差分积分放大器; 以及切换电路，用于将所述差分一端电容器的第一电容器充电到所述差分一端电容器的第一电容器和所述差分一端电容器的第二电容器到第一相位的第二电压电平，所述第二相位将所述第一电容器连接到所述 第一求和节点和所述第二电容器到所述放大器的所述第二求和节点，以在第三阶段提供基本上代表所述第一和第二电压电平与所述输入共模电压之间的差的第一和第二输出变化， 所述第二电压电平和所述第二电容器达到所述第一电压电平，并且在将所述第一电容器与所述第二求和节点和所述第二电容器连接到所述放大器的所述第一求和节点的第四阶段中，以提供基本上代表 所述第一和第二电压电平与所述输入共模之间的差 电压，组合的第一，第二，第三和第四变化表示所述第一和第二电容器的电容基本上独立于所述输入共模电压。
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公开(公告)号：US07235983B2
公开(公告)日：2007-06-26
申请号：US11370764
申请日：2006-03-08
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.
摘要翻译： 用于感测电容器的电容的单端电容器接口电路包括具有输入共模电压的差分积分放大器和电压基本上等于输入共模电压的两个求和节点，用于将电容器充电到第一 电压电平在第一阶段中，在第二阶段将电容器连接到差分放大器的求和节点之一，以提供基本上代表第一电压电平和输入共模电压之间的差的第一输出变化，以及 也代表电容器; 在第三相中将电容器充电到第二电压电平，并且在第四相中将电容器连接到差分放大器的另一个求和节点，以提供基本上代表第二电压电平与第二电压之间的差的第二输出变化 输入共模电压，也代表电容器; 组合的第一和第二输出变化表示电容器的电容基本上独立于输入共模电压。
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17.发明授权Method of invoking a power-down mode on an integrated circuit by monitoring a normally changing input signal 失效通过监视正常变化的输入信号在集成电路上调用掉电模式的方法
公开(公告)号：US6147528A
公开(公告)日：2000-11-14
申请号：US41937
申请日：1998-03-13
申请人： John O'Dowd , John Wynne
发明人： John O'Dowd , John Wynne
CPC分类号： G06F1/3287 , G06F1/24 , G06F1/3203 , Y02B60/1282
摘要： An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.
摘要翻译： 集成电路包括响应于集成电路的输入处的正常变化的信号以实现电路的主要功能的装置，以及用于在集成电路的问题的输入端监视该正常变化的信号的装置。 该监视装置响应于暂停正常变化的信号以传送信号以实现电路的次要功能。 在示例性实施例中，本发明旨在实现电路的掉电，而不使用明确的掉电或复位引脚。 通常以最小速率变化的输入信号，例如， 优选地，时钟信号被保持在固定状态一个最小持续时间以调用复位或掉电模式。 因此，集成电路可以在没有明显的掉电或复位引脚可用的情况下掉电或复位。
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公开(公告)号：US20130180879A1
公开(公告)日：2013-07-18
申请号：US13350587
申请日：2012-01-13
申请人： John O'Dowd , Canay Tulunay Riordan
发明人： John O'Dowd , Canay Tulunay Riordan
CPC分类号： G06F1/1628 , G06F1/1632 , H04M1/185
摘要： A case assembly for a portable device is provided that has a first sleeve member, a second sleeve member and a customized plate member. The first sleeve member is mated with the second sleeve member to encase the portable device. The customized plate member is configured and arranged to connect with the first sleeve member and the second sleeve member.
摘要翻译： 提供了一种用于便携式设备的壳体组件，其具有第一套筒构件，第二套筒构件和定制板构件。 第一套筒构件与第二套筒构件配合以封装便携式装置。 定制的板构件被构造和布置成与第一套筒构件和第二套筒构件连接。
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19.发明授权公开(公告)号：US07656330B2
公开(公告)日：2010-02-02
申请号：US12154330
申请日：2008-05-22
申请人： John O'Dowd , Kevin Jennings , Tadhg Creedon
发明人： John O'Dowd , Kevin Jennings , Tadhg Creedon
IPC分类号： H03M3/00
CPC分类号： H03M1/181
摘要： Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.
摘要翻译： 模数转换器（ADC）的自动量程移位包括组合外部模拟输入和DAC输出以向ADC提供输入，检测ADC的输出范围是否高于预定的上限范围或低于 并且如果ADC输出高于上限范围限制，则产生调整代码以增加DAC输出，并且如果ADC输出低于ADC输出的下限范围以减小DAC输出，则在ADC输出 高于上限，并且当ADC输出低于下限以增加ADC输入，以将ADC输入保持在ADC范围内。
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20.发明申请公开(公告)号：US20080291067A1
公开(公告)日：2008-11-27
申请号：US12154330
申请日：2008-05-22
申请人： John O'Dowd , Kevin Jennings , Tadhg Creedon
发明人： John O'Dowd , Kevin Jennings , Tadhg Creedon
CPC分类号： H03M1/181
摘要： Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.
摘要翻译： 模数转换器（ADC）的自动量程移位包括组合外部模拟输入和DAC输出以向ADC提供输入，检测ADC的输出范围是否高于预定的上限范围或低于 并且如果ADC输出高于上限范围限制，则产生调整代码以增加DAC输出，并且如果ADC输出低于ADC输出的下限范围以减小DAC输出，则在ADC输出 高于上限，并且当ADC输出低于下限以增加ADC输入，以将ADC输入保持在ADC范围内。
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