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公开(公告)号：US06834084B2
公开(公告)日：2004-12-21
申请号：US10139560
申请日：2002-05-06
IPC分类号： H04L2549
CPC分类号： H03C3/222
摘要： A polar modulator creates an amplitude signal and a frequency signal and digitally adjusts the signals so that the frequency and amplitude signals arrive at the power amplifier at the appropriate times. A digital predistortion filter is applied to the frequency signal. The frequency signal is then provided to a single port of a fractional N divider in a phase locked loop. The output of the phase locked loop drives an input of the power amplifier while the amplitude signal is converted to an analog signal and controls the power supply input of the power amplifier.
摘要翻译： 极性调制器产生振幅信号和频率信号，并对信号进行数字调节，使得频率和振幅信号在适当的时间到达功率放大器。 数字预失真滤波器应用于频率信号。 然后将频率信号提供给锁相环中的分数N分频器的单个端口。 锁相环的输出驱动功率放大器的输入，同时将幅度信号转换为模拟信号，并控制功率放大器的电源输入。
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12.发明授权Saturation correction without using saturation detection and saturation prevention for a power amplifier 有权饱和度校正，无需对功率放大器进行饱和检测和饱和度预防公开(公告)号：US08874050B1
公开(公告)日：2014-10-28
申请号：US12774155
申请日：2010-05-05
IPC分类号： H01Q11/12
CPC分类号： H01P5/184 , H03F1/0211 , H03F3/195 , H03F3/24 , H03F3/68 , H03F2200/541 , H03H7/38
摘要： A circuit and method for a saturation correction of a power amplifier (PA) is provided in order to maintain a desirable switching spectrum. The circuit includes a closed loop system that is responsive to a dynamic PA control signal known as VRAMP. The method samples a detector voltage that represents the output of the PA at the maximum voltage level of VRAMP. The sampled detector voltage is then reduced by a predetermined amount and applied as a fixed voltage PA control signal in the place of VRAMP. As a result, the closed loop system responds to the fixed voltage PA control signal to bring the PA out of saturation before VRAMP can begin a voltage decrease. Once the VRAMP voltage decreases, VRAMP is reapplied as a dynamic PA control signal in place of the fixed voltage control signal.
摘要翻译： 提供了用于功率放大器（PA）的饱和校正的电路和方法，以便保持期望的开关频谱。 电路包括响应于称为VRAMP的动态PA控制信号的闭环系统。 该方法对在VRAMP的最大电压电平下表示PA输出的检测器电压进行采样。 然后将取样的检测器电压减小预定量并作为固定电压PA控制信号施加在VRAMP的位置。 结果，闭环系统响应于固定电压PA控制信号，使得在VRAMP可以开始降压之前使PA失去饱和。 一旦VRAMP电压降低，VRAMP将重新应用为动态PA控制信号，代替固定电压控制信号。
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13.发明申请公开(公告)号：US20120281597A1
公开(公告)日：2012-11-08
申请号：US13460861
申请日：2012-05-01
CPC分类号： H04B1/0067 , H03F1/02 , H03F1/0227 , H03F3/24 , H03F3/68 , H03F3/72 , H03F2203/7209 , H03F2203/7221 , H04B2001/045 , H04L5/001
摘要： A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA and a first-second PA, and a second PA block having a second-first PA and a second-second PA. First and second modulated switchers are adapted to selectively supply power to the first-first PA and the second-first PA, and to supply power to the first-second PA and the second-second PA, respectively. The first and second modulated switchers have a modulation bandwidth of at least 20 MHz and are both suitable for envelope tracking modulation. A control system is adapted to selectively enable and disable the first-first PA, first-second PA, the second-first PA, and the second-second PA. First and second switches are responsive to control signals to route carriers and received signals between first and second antennas depending upon a selectable mode of operation such as intra-band or inter-band operation.
摘要翻译： 公开了具有电源管理的前端无线电架构（FERA）。 FERA包括具有第一第一PA和第一秒PA的第一功率放大器（PA）块和具有第二第一PA和第二秒PA的第二PA块。 第一和第二调制切换器适于选择性地向第一优先PA和第二第一PA供电，并分别向第一秒PA和第二秒PA供电。 第一和第二调制切换器具有至少20MHz的调制带宽，并且都适用于包络跟踪调制。 控制系统适于选择性地启用和禁用第一优先PA，第一秒PA，第二优先PA和第二秒PA。 第一和第二开关响应于控制信号以根据诸如带内或频带间操作的可选择的操作模式在第一和第二天线之间路由载波和接收信号。
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公开(公告)号：US08275330B1
公开(公告)日：2012-09-25
申请号：US12895255
申请日：2010-09-30
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： The present disclosure relates to IQ modulation circuitry that during a data burst mode, modulates an RF carrier signal to provide a modulated RF signal, which is used for transmission of a transmit slot. During the data burst mode, a maximum energy spectrum peak of the modulated RF signal is about coincident with an RF carrier frequency of the RF carrier signal to comply with communications protocols. Further, during an energy-shifted ramp-down mode, which is coincident with ramp-down of the modulated RF signal, the IQ modulation circuitry modulates the RF carrier signal to provide the modulated RF signal. During the energy-shifted ramp-down mode, the maximum energy spectrum peak of the modulated RF signal is shifted away from the RF carrier frequency of the RF carrier signal to mitigate the effects of preparing for receiving an RF receive signal.
摘要翻译： 本公开涉及IQ调制电路，其在数据突发模式期间，调制RF载波信号以提供用于传输发射时隙的调制RF信号。 在数据突发模式期间，调制的RF信号的最大能谱峰值与RF载波信号的RF载波频率大致一致，以符合通信协议。 此外，在与调制的RF信号的斜降一致的能量偏移斜降模式期间，IQ调制电路调制RF载波信号以提供经调制的RF信号。 在能量偏移斜降模式期间，调制的RF信号的最大能谱峰值偏离RF载波信号的RF载波频率，以减轻准备接收RF接收信号的影响。
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公开(公告)号：US20120200473A1
公开(公告)日：2012-08-09
申请号：US13022840
申请日：2011-02-08
IPC分类号： H01Q3/24
CPC分类号： H04B1/48
摘要： The exemplary embodiments include a radio frequency antenna switch configured to reject harmonic frequencies. In addition, the harmonic-rejected radio frequencies of the radio frequency antenna switch may be tuned by use of a capacitor array. The capacitor array may be configured with fuse elements or by control logic.
摘要翻译： 示例性实施例包括被配置为拒绝谐波频率的射频天线开关。 此外，射频天线开关的谐波抑制无线电频率可以通过使用电容器阵列进行调谐。 电容器阵列可以由熔丝元件或控制逻辑构成。
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公开(公告)号：US08193859B1
公开(公告)日：2012-06-05
申请号：US12882313
申请日：2010-09-15
IPC分类号： H03G3/20
CPC分类号： H03G3/3042
摘要： A dual FET detector having a common RF input and a common detector output for two detector circuits is provided. The first detector circuit is optimized for detecting lower RF signal levels while the second detector circuit is optimized for detecting higher RF signal levels. A detector output voltage output from the common detector output is a composite signal made up of the individual contributions of the two detector circuits. A control circuit receives a feedback signal derived from the detector output voltage, and uses the feedback signal to control a transition between urging a predominance of the contribution to the detector output voltage from one of the detector circuits to the other. The control of the transition between the detector circuits ensures that whichever of the two detector circuits is best optimized for a particular RF signal level will contribute the most to the detector output voltage.
摘要翻译： 提供具有公共RF输入和用于两个检测器电路的公共检测器输出的双FET检测器。 第一检测器电路被优化用于检测较低的RF信号电平，而第二检测器电路被优化用于检测更高的RF信号电平。 从公共检测器输出输出的检测器输出电压是由两个检测器电路的各自贡献组成的复合信号。 控制电路接收从检测器输出电压导出的反馈信号，并且使用反馈信号来控制在从检测器电路之一到检测器电路之间的对检测器输出电压的贡献的主导之间的转变。 对检测器电路之间的转换的控制确保两个检测器电路中的任一个针对特定的RF信号电平进行最佳优化，将对检测器的输出电压贡献最大。
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公开(公告)号：US20110291857A1
公开(公告)日：2011-12-01
申请号：US13150346
申请日：2011-06-01
IPC分类号： G01D18/00
CPC分类号： H03F1/0233 , H03F1/0222 , H03F1/32 , H03F3/19 , H03F3/24 , H03F3/245 , H03F2200/451 , H03F2200/465
摘要： The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector.
摘要翻译： 示例性实施例包括基于非线性功率检测器输出和相关联的功率放大器输出电平的测量以及一组数据点的方法，计算机可读介质和用于校准射频设备的非线性功率检测器的设备 其特征在于标称非线性功率检测器。 表征标称非线性功率检测器的数据点集合作为标称功率检测器输出数据存储在校准系统存储器中。 测量的非线性功率检测器输出，功率放大器输出电平和额定功率检测器输出数据用于确定功率检测器误差函数，其表征非线性功率检测器的响应与标称非线性 功率检测器 功率检测器误差函数和标称功率检测器输出数据用于开发存储在非线性功率检测器中的校准功率检测器输出数据组。
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18.发明授权System and method for transitioning between modulation formats in adjacent bursts triggering on data flow 有权用于在相邻突发中的调制格式之间转换以触发数据流的系统和方法公开(公告)号：US07277497B2
公开(公告)日：2007-10-02
申请号：US10985207
申请日：2004-11-10
CPC分类号： H04L27/2017 , H04L27/0008
摘要： A system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The system includes a modulation system having a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition between a first transmit burst in the first modulation format and a second transmit burst in the second modulation format, the data interface receives a timing signal signifying a start of data for the second transmit burst. In response to the timing signal, the second modulation circuitry resets, and the data interface delays the data for the second transmit burst by a modulator delay time. By delaying the data for the second transmit burst, a glitch caused by resetting the second modulation circuitry arrives at the output of the second modulation circuitry prior to the data for the second transmit burst.
摘要翻译： 提供了一种用于在相邻发射脉冲串中的调制格式之间转换的系统和方法。 该系统包括具有数据接口的调制系统，根据第一调制格式操作的第一调制电路和根据第二调制格式操作的第二调制电路。 在第一调制格式的第一发送突发与第二调制格式的第二发送突发之间的转换期间，数据接口接收表示第二发送突发的数据开始的定时信号。 响应于定时信号，第二调制电路复位，并且数据接口将第二发射脉冲串的数据延迟调制器延迟时间。 通过延迟第二发送脉冲串的数据，由第二调制电路复位引起的毛刺在第二发射脉冲串的数据之前到达第二调制电路的输出端。
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19.发明授权公开(公告)号：US07251298B1
公开(公告)日：2007-07-31
申请号：US10644231
申请日：2003-08-20
摘要： The present invention provides a receiver frontend that eliminates static and dynamic DC errors and has improved second order intermodulation distortion (IMD2) performance. The receiver frontend includes a first mixer that multiplies a received signal and a first local oscillator (LO) signal to produce an intermediate frequency (IF) signal. A second mixer multiplies the IF signal and a second LO signal to produce an output signal. A first divider circuit divides a reference signal from a reference oscillator by a first divisor N to produce the first LO signal, and a second divider circuit divides the reference signal by a second divisor M to produce the second LO signal. Preferably, the first and second divisors N and M are each integers greater than one (1), and the second divisor M is not an integer multiple of the first divisor N.
摘要翻译： 本发明提供一种消除静态和动态DC误差并具有改进的二阶互调失真（IMD2）性能的接收器前端。 接收器前端包括将接收信号和第一本地振荡器（LO）信号相乘以产生中频（IF）信号的第一混频器。 第二混频器将IF信号和第二LO信号相乘以产生输出信号。 第一除法器电路将来自参考振荡器的参考信号由第一除数N分频以产生第一LO信号，并且第二除法器电路将参考信号除以第二除数M以产生第二LO信号。 优选地，第一和第二因子N和M各自是大于1（1）的整数，并且第二因子M不是第一因子N的整数倍。
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公开(公告)号：US5867063A
公开(公告)日：1999-02-02
申请号：US760767
申请日：1996-12-05
IPC分类号： H03G3/30
CPC分类号： H03G3/3068
摘要： A system (100 or 200) includes a first AGC stage (102) having a programming input and a gain input. A second AGC stage (104 or 210 and 234) is coupled in a common path with the first AGC stage, the second AGC stage having a programming input and a gain input. The first and second AGC stages are programmed by respective programming signals to produce independent gain characteristics responsive to a common gain signal at their respective gain inputs.
摘要翻译： 系统（100或200）包括具有编程输入和增益输入的第一AGC级（102）。 第二AGC级（104或210和234）与第一AGC级共同路径耦合，第二AGC级具有编程输入和增益输入。 第一和第二AGC级由相应的编程信号编程，以响应于它们各自的增益输入处的公共增益信号产生独立的增益特性。
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