公开(公告)号：US07645644B2

公开(公告)日：2010-01-12

申请号：US12113994

申请日：2008-05-02

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L21/82

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/1052

摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n

摘要翻译： 在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。 。 。 n，n + 1，。 。 。 ，m-1，m}，其中M，n和m是正整数，并且其中n

公开(公告)号：US07605430B2

公开(公告)日：2009-10-20

申请号：US11474699

申请日：2006-06-23

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

摘要翻译： 非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。 翅片形有源区形成在器件隔离层的各部分之间。 侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。 因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。 侧壁保护层可以使用器件隔离层形成。 或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

公开(公告)号：US20070104011A1

公开(公告)日：2007-05-10

申请号：US11507511

申请日：2006-08-22

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Chang-Hyun Lee ,  Jang-Sik Lee ,  Vie-Na Kim

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Chang-Hyun Lee ,  Jang-Sik Lee ,  Vie-Na Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/14 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.

摘要翻译： 电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于 与第一区域的顶表面不同的水平。 单元阵列还包括跨越第一区域的多个字线。 单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

公开(公告)号：US20060289944A1

公开(公告)日：2006-12-28

申请号：US11474699

申请日：2006-06-23

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

公开(公告)号：US08329574B2

公开(公告)日：2012-12-11

申请号：US13230978

申请日：2011-09-13

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L21/44

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S257/905

摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

摘要翻译： 闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。 亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。 位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。 在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

公开(公告)号：US08198157B2

公开(公告)日：2012-06-12

申请号：US13236913

申请日：2011-09-20

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： H01L21/82 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

公开(公告)号：US20120045890A1

公开(公告)日：2012-02-23

申请号：US13236913

申请日：2011-09-20

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： H01L21/28

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

公开(公告)号：US07884425B2

公开(公告)日：2011-02-08

申请号：US12257939

申请日：2008-10-24

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric.

摘要翻译： 在一个实施例中，半导体存储器件包括具有第一和第二有源区的衬底。 第一有源区包括第一源区和漏区，第二有源区包括第二源区和漏区。 第一层间电介质位于衬底上。 第一导电结构延伸穿过第一层间电介质。 第一位线位于第一层间电介质上。 第二层间电介质在第一层间电介质上。 接触孔延伸穿过第二和第一层间电介质。 该装置包括接触孔内的第二导电结构并且延伸穿过第一和第二层间电介质。 第二位线位于第二层间电介质上。 第二层间电介质的底部处的接触孔的宽度小于或基本上等于第二层间电介质顶部的宽度。

公开(公告)号：US07881114B2

公开(公告)日：2011-02-01

申请号：US12340250

申请日：2008-12-19

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

公开(公告)号：US07723776B2

公开(公告)日：2010-05-25

申请号：US11376371

申请日：2006-03-15

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S257/905

摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

摘要翻译： 闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。 亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。 位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。 在远离副有源区域的位线接触插头上提供细长的位线并且电接触。