公开(公告)号：US5168555A

公开(公告)日：1992-12-01

申请号：US403637

申请日：1989-09-06

申请人： Larry L. Byers ,  Joseba M. Desubijana

发明人： Larry L. Byers ,  Joseba M. Desubijana

IPC分类号： G06F9/445 ,  G06F15/177

CPC分类号： G06F15/177 ,  G06F9/4405

摘要： A multi-processing system of the type having a plurality of MSUs is provided with a support controller in each MSU. Each of the MSUs is provided with a plurality of the interface registers, one for each associated MSU to be connected to the master MSU. Each support controller in each MSU is provided with an initial program load (IPL) controller and each IPL controller is provided with a scan settable control coupled to an external keyboard or console which permits unique scan settable information to be loaded into the IPL controller for setting the interface registers and for interconnecting the MSUs in a desired multi-processing configuration.

摘要翻译： 具有多个MSU的多处理系统在每个MSU中设置有支持控制器。 每个MSU设置有多个接口寄存器，每个相关联的MSU一个用于连接到主MSU。 每个MSU中的每个支持控制器具有初始程序加载（IPL）控制器，并且每个IPL控制器被提供有耦合到外部键盘或控制台的扫描可设置控制器，其允许将唯一的可扫描可设置信息加载到IPL控制器中用于设置 接口注册并用于以期望的多处理配置来互连MSU。

公开(公告)号：US5524218A

公开(公告)日：1996-06-04

申请号：US172652

申请日：1993-12-23

申请人： Larry L. Byers ,  Donald M. Davies ,  Joseba M. Desubijana ,  Michael E. Mayer ,  Randall L. Piper ,  Lloyd E. Thorsbakken ,  Steven M. Wierdsma

发明人： Larry L. Byers ,  Donald M. Davies ,  Joseba M. Desubijana ,  Michael E. Mayer ,  Randall L. Piper ,  Lloyd E. Thorsbakken ,  Steven M. Wierdsma

IPC分类号： G06F3/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/12 ,  H04B10/00 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  G06F12/0866 ,  G06F13/128 ,  H04L69/324

摘要： A system for communicating data between a main processor and a peripheral processor over a fiber optic interface. The interface is a dedicated, point-to-point link operating in full-duplex, asynchronous mode. Dual fibers and physical layer controllers are used in a cascaded fashion to double the throughput of the interface. Frame control logic coordinates formatting of data into frames for transmission over the interface. Frame format and interface protocol are based on FDDI, but are improved to more efficiently transfer data in a point-to-point implementation. Frame Check Sequences are generated and verified to ensure error-free data transfers. Frame sending and frame receiving logic communicate with the main and peripheral processors, accepting data transfer requests and forwarding received data.

摘要翻译： 一种用于通过光纤接口在主处理器和外围处理器之间传送数据的系统。 该接口是以全双工，异步模式运行的专用点对点链路。 双光纤和物理层控制器以级联方式使用，使接口的吞吐量加倍。 帧控制逻辑将数据格式化为帧以便通过接口传输。 帧格式和接口协议基于FDDI，但是在点对点实现中被改进以更有效地传输数据。 帧检查序列生成和验证，以确保无错误的数据传输。 帧发送和帧接收逻辑与主处理器和外围处理器通信，接受数据传输请求和转发接收的数据。

公开(公告)号：US5784712A

公开(公告)日：1998-07-21

申请号：US396677

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

IPC分类号： G06F9/312 ,  G06F9/345 ,  G06F13/16 ,  G06F9/32

CPC分类号： G06F9/30043 ,  G06F13/1631 ,  G06F9/345 ,  G06F9/3861

摘要： A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

摘要翻译： 一种用于有效地读取或写入存储器内的多个连续地址位置的方法和装置。 在示例性实施例中，当访问连续的地址位置时，可能不需要处理器等来为每个读取和/或写入操作向存储器单元提供地址。 也就是说，对于访问连续地址位置的多个存储器访问，处理器等可以提供初始地址，但此后可能不需要向存储器单元提供后续地址。 随后的地址可以由自动增量块自动生成。

公开(公告)号：US5784393A

公开(公告)日：1998-07-21

申请号：US396680

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Ronald W. Splett

发明人： Larry L. Byers ,  Gary R. Robeck ,  Ronald W. Splett

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： A method and apparatus for providing fault detection to a corresponding bus when one or more of the users connected to the bus does not have a fault detection capability provided therein. Further, the present invention may provide a method and apparatus for performing fault detection on a corresponding bus when the width of the bus is insufficient to accommodate a number of parity bits. In an exemplary embodiment, a selected one of the number of users may validate all bus transmissions via a number of transceivers, regardless of which user has a fault detection capability provided therein. In another exemplary embodiment of the present invention, a transmitting user may provide a data word and a number of corresponding parity bits. The transmitting user may provide the data word to the bus while storing the corresponding number of parity bits therein. The data word may be provided back to the transmitting user via the corresponding transceivers wherein the transmitting user may check the data word against the number of parity bits previously generated by the transmitting user.

摘要翻译： 当连接到总线的一个或多个用户不具有其中提供的故障检测能力时，向相应总线提供故障检测的方法和装置。 此外，本发明可以提供一种用于当总线的宽度不足以容纳多个奇偶校验位时在相应总线上执行故障检测的方法和装置。 在示例性实施例中，所选择的一个用户可以经由多个收发器验证所有总线传输，而不管哪个用户具有其中提供的故障检测能力。 在本发明的另一示例性实施例中，发送用户可以提供数据字和多个对应的奇偶校验位。 发送用户可以在存储相应数量的奇偶校验位的同时向总线提供数据字。 数据字可以经由相应的收发器提供给发送用户，其中发送用户可以根据发送用户先前生成的奇偶校验位的数量来检查数据字。

公开(公告)号：US5680537A

公开(公告)日：1997-10-21

申请号：US396678

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

IPC分类号： G06F11/22 ,  G06F13/00

CPC分类号： G06F11/2268

摘要： A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.

摘要翻译： 一种用于隔离具有通过接口设备访问用户的控制器等的系统中的错误的方法和装置。 控制器等可以经由第一总线耦合到接口设备，并且接口设备可以经由第二总线耦合到用户。 控制器等可以通过接口设备检测从用户到控制器的数据传输中的错误，并且可以将错误与第二总线/接口设备或第一总线/控制器隔离。 这种前期错误隔离可以减少在从系统移除相应的PC板等之后服务技术人员所需的分析量，从而降低其成本。

公开(公告)号：US06457067B1

公开(公告)日：2002-09-24

申请号：US09216303

申请日：1998-12-18

申请人： Larry L. Byers ,  Jerome G. Carlin ,  Michael R. Overley ,  Gary R. Robeck ,  Lloyd E. Thorsbakken

发明人： Larry L. Byers ,  Jerome G. Carlin ,  Michael R. Overley ,  Gary R. Robeck ,  Lloyd E. Thorsbakken

IPC分类号： G06F300

CPC分类号： G11C29/024 ,  G11C29/02

摘要： An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.

摘要翻译： 提供了一种用于检测存储设备的寻址逻辑内的故障发生的改进的故障检测系统和方法。 存储到存储设备内的所选地址的数据包括所选地址的副本。 在随后的读取操作期间，从存储器读取地址的副本，并与用于执行存储器访问的读取地址进行比较。 如果地址不一致，则在存储设备的控制逻辑内发生潜在寻址故障。 故障检测系统特别适用于具有相对较少数量可寻址位置的存储设备，每个存储设备包含相对大量的位。 根据本发明的一个实施例，存储设备是用作队列的通用寄存器阵列（GRA）。

公开(公告)号：US5828823A

公开(公告)日：1998-10-27

申请号：US845643

申请日：1997-04-25

申请人： Larry L. Byers ,  Gary R. Robeck

发明人： Larry L. Byers ,  Gary R. Robeck

IPC分类号： G06F11/14 ,  G06F12/16

CPC分类号： G06F11/1441

摘要： A method and apparatus for efficiently download and/or upload critical data elements between a computer's memory to/from a data save disk system, when a failure of a primary power source is detected. This is accomplished by coupling the data save disk system directly to the memory module such that the data elements in the memory module may be downloaded directly to the data save disk system without any intervention by a host computer. This configuration may have a number of advantages. First, the speed at which the data elements may be downloaded from the memory module to the data save disk system may be enhanced due to the direct coupling therebetween. Second, significant power savings may be realized because only the memory module and the data save disk system need to be powered by a secondary power source to effect the download operation. This may significantly increase the amount of time that the secondary power source may power the system thereby increasing the number of data elements that can be downloaded from the memory.

摘要翻译： 当检测到主电源的故障时，用于在数据存储盘系统的计算机存储器之间有效地下载和/或上传关键数据元素的方法和装置。 这是通过将数据保存磁盘系统直接耦合到存储器模块来实现的，使得存储器模块中的数据元素可以直接下载到数据保存磁盘系统，而无需主计算机的任何干预。 该配置可以具有许多优点。 首先，可以通过它们之间的直接耦合来增强数据元素可以从存储器模块下载到数据保存盘系统的速度。 第二，可以实现显着的功率节省，因为只有存储器模块和数据保存磁盘系统需要由次级电源供电才能实现下载操作。 这可以显着增加次级电源可以为系统供电的时间量，从而增加可以从存储器下载的数据元素的数量。

公开(公告)号：US5784382A

公开(公告)日：1998-07-21

申请号：US396679

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  Randy L. DeGarmo ,  Paul A. LaBerge

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  Randy L. DeGarmo ,  Paul A. LaBerge

IPC分类号： G11C29/20 ,  G01R31/28 ,  G06F12/00

CPC分类号： G11C29/20

摘要： A method and apparatus for increasing the efficiency of a dynamic read and/or write operation of a memory element within a computer system. The dynamic read and/or write operation may be performed when the computer system is in a functional mode or a test mode. The present invention may reduce the number of bits that are required to be serially shifted into a design by providing an auto-increment block. It is recognized that most multi-word access to a memory are made to sequential address locations within the memory. The auto-increment block takes advantage of this and automatically manipulates the address thereby not requiring subsequent addresses to be serially shifted into the design. Further, the control word may be stored within the design for subsequent accesses. That is, the support controller may shift a starting address and a control word into the design. The addresses for subsequent accesses may be generated by the auto-increment block, thereby only requiring that the support controller shift a data word to/from the design. This may significantly reduce the time necessary perform the subsequent read and/or write operations.

摘要翻译： 一种用于提高计算机系统内的存储元件的动态读取和/或写入操作的效率的方法和装置。 当计算机系统处于功能模式或测试模式时，可以执行动态读取和/或写入操作。 本发明可以通过提供自动增量块来减少串行转换到设计中所需的位数。 可以认识到，大多数对存储器的多字访问是对存储器内的顺序地址位置进行的。 自动增量块利用此功能，并自动操作地址，从而不需要将后续地址串行转换到设计中。 此外，控制字可以存储在设计中用于随后的访问。 也就是说，支持控制器可以将起始地址和控制字转移到设计中。 用于后续访问的地址可以由自动递增块生成，从而仅需要支持控制器将数据字移向/从设计。 这可能会显着减少执行后续读取和/或写入操作所需的时间。

公开(公告)号：US5596716A

公开(公告)日：1997-01-21

申请号：US396953

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

IPC分类号： G06F11/07 ,  G06F11/22 ,  G06F11/08 ,  G06F11/14

CPC分类号： G06F11/0772 ,  G06F11/0721 ,  G06F11/22

摘要： A method and apparatus for efficiently identifying and indicating the severity of the fault within a computer system. In an exemplary embodiment of the present invention, the circuitry of a computer system may be divided into a number of groups. Each group may contain circuitry which may result in the same fault type. For example, predetermined circuitry which, when a fault is detected therein, may have a minimal affect on the normal operation of the computer system may be provided in a first group. Similarly, predetermined circuitry which, when a fault is detected therein, may have an immediate affect on the normal operation of the computer system may be provided in a second group. Each group may provide an error priority signal to a support controller. The support controller may interpret the number of error priority signals provided by the number of groups and may determine the appropriate time to take corrective action thereon.

摘要翻译： 一种用于有效地识别和指示计算机系统内的故障严重性的方法和装置。 在本发明的示例性实施例中，计算机系统的电路可以被划分成多个组。 每个组可能包含可能导致相同故障类型的电路。 例如，当在其中检测到故障时可能对计算机系统的正常操作具有最小影响的预定电路可以在第一组中提供。 类似地，当在其中检测到故障时可能对计算机系统的正常操作具有直接影响的预定电路可以在第二组中提供。 每个组可以向支持控制器提供错误优先级信号。 支持控制器可以解释由组数提供的错误优先级信号的数量，并且可以确定在其上采取校正动作的适当时间。

公开(公告)号：US5511164A

公开(公告)日：1996-04-23

申请号：US396952

申请日：1995-03-01

申请人： Terry J. Brunmeier ,  Larry L. Byers ,  John A. Miller ,  Gary R. Robeck

发明人： Terry J. Brunmeier ,  Larry L. Byers ,  John A. Miller ,  Gary R. Robeck

IPC分类号： G06F11/07 ,  G06F11/00

CPC分类号： G06F11/073 ,  G06F11/0793

摘要： A method and apparatus for identify the source and nature of an error, without aborting the operation of the computer system. In one embodiment of the present invention, the source of the error may be a hardware element and the nature of the error may be identified as either fatal or non-fatal. If the nature of the error is considered non-fatal, the present invention may correct the error and continue the operation of the computer system. This may allow detected errors to be handled immediately after they occur, rather than aborting the operation of the computer system and waiting for a support controller or the like to analyze the error. This may significantly enhance the reliability and performance of a corresponding computer system. This may be especially important during time critical operations. Further, since the operation of the computer system may be aborted a fewer number of times, the present invention may minimize the amount of data loss. This may be particularly important for high reliability computer applications, including banking applications and airline reservation applications, where the integrity of the data base is of the utmost importance.

摘要翻译： 用于识别错误的来源和性质的方法和装置，而不中止计算机系统的操作。 在本发明的一个实施例中，错误的来源可以是硬件元件，并且错误的性质可以被识别为致命的或非致命的。 如果错误的性质被认为是非致命的，则本发明可以纠正错误并继续计算机系统的操作。 这可以允许检测到的错误在它们发生之后立即被处理，而不是中止计算机系统的操作并等待支持控制器等来分析错误。 这可以显着提高相应计算机系统的可靠性和性能。 这在时间关键操作中可能尤其重要。 此外，由于计算机系统的操作可以中止更少的次数，本发明可以最小化数据丢失的量。 这对于可靠性高的计算机应用尤其重要，包括银行应用和航空预订应用，数据库的完整性至关重要。