公开(公告)号：US20240223211A1

公开(公告)日：2024-07-04

申请号：US18536057

申请日：2023-12-11

申请人： Kioxia Corporation

发明人： Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Sho KODAMA

IPC分类号： H03M7/40 ,  H03M7/30

CPC分类号： H03M7/4093 ,  H03M7/3077 ,  H03M7/3088 ,  H03M7/6005 ,  H03M7/6011 ,  H03M7/6023

摘要： According to one embodiment, a conversion device includes a demultiplexer, first to Nth extractors and a deinterleave unit. The demultiplexer extracts first to Nth substreams from a first compressed stream. The first to Nth substreams are placed in order in the first compressed stream and include first variable-length codes to Nth variable-length codes into which first symbols to Nth symbols of a symbol string have been converted. The first to Nth extractors extract the first variable-length codes to the Nth variable-length codes from the first to Nth substreams. The deinterleave unit reorders the first variable-length codes to the Nth variable-length codes in accordance with the symbol string and outputs a second compressed stream.

公开(公告)号：US20230403027A1

公开(公告)日：2023-12-14

申请号：US18118732

申请日：2023-03-07

申请人： Kioxia Corporation

发明人： Keiri NAKANISHI ,  Sho KODAMA ,  Daisuke YASHIMA

IPC分类号： H03M7/30 ,  H03M7/40

CPC分类号： H03M7/3088 ,  H03M7/4031

摘要： According to one embodiment, a dictionary compressor for compressing input first data includes a buffer and a search unit. The buffer stores data input to the dictionary compressor prior to the first data.
The search unit acquires, from the first data, partial data strings each having a first data length and having head positions in the first data, respectively, that are sequentially shifted by a second data length shorter than the first data length. The search unit performs search processes in parallel and acquires search results respectively corresponding to the search processes, the search processes searching the buffer to acquire respective match data strings that at least partially match the partial data strings, respectively.

公开(公告)号：US20230087517A1

公开(公告)日：2023-03-23

申请号：US17680128

申请日：2022-02-24

申请人： KIOXIA CORPORATION

发明人： Kohei OIKAWA ,  Keiri NAKANISHI ,  Sho KODAMA ,  Masato SUMIYOSHI ,  Daisuke YASHIMA ,  Youhei FUKAZAWA ,  Zheye WANG ,  Takashi MIURA

IPC分类号： H03M13/09 ,  H03M13/00

摘要： A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

公开(公告)号：US20220255556A1

公开(公告)日：2022-08-11

申请号：US17472431

申请日：2021-09-10

申请人： Kioxia Corporation

发明人： Daisuke YASHIMA ,  Kohei OIKAWA ,  Sho KODAMA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Youhei FUKAZAWA ,  Zheye WANG ,  Takashi MIURA

IPC分类号： H03M7/30 ,  G06F3/06

摘要： According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

公开(公告)号：US20220083282A1

公开(公告)日：2022-03-17

申请号：US17191845

申请日：2021-03-04

申请人： Kioxia Corporation

发明人： Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Sho KODAMA ,  Kohei OIKAWA

IPC分类号： G06F3/06 ,  H03M7/30

摘要： A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.

公开(公告)号：US20240303188A1

公开(公告)日：2024-09-12

申请号：US18593215

申请日：2024-03-01

申请人： Kioxia Corporation

发明人： Takashi TAKEMOTO ,  Kensaku YAMAGUCHI ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Sho KODAMA

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0253 ,  G06F2212/7201

摘要： A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.

公开(公告)号：US20230081961A1

公开(公告)日：2023-03-16

申请号：US17693606

申请日：2022-03-14

申请人： Kioxia Corporation

发明人： Sho KODAMA ,  Keiri NAKANISHI ,  Daisuke YASHIMA

IPC分类号： H03M7/30 ,  G06F3/06 ,  H03M7/40

摘要： According to one embodiment, a compression circuit generates substrings from input data for (3+M) cycles, the input data being N bytes per cycle, a byte length of each substring being greater than or equal to (N×(1+M)+1); obtains a set of matches, each of the matches including at least one past input data which input past and corresponds to at least a part of each of the substrings; selects a subset of matches from the set of matches including the input data of one cycle; and outputs the subset of matches. M is zero or a natural number. N is a positive integer which is two or more.

公开(公告)号：US20230070623A1

公开(公告)日：2023-03-09

申请号：US17653513

申请日：2022-03-04

申请人： Kioxia Corporation

发明人： Daisuke YASHIMA ,  Youhei FUKAZAWA ,  Sho KODAMA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Kohei OIKAWA ,  Zheye WANG ,  Takashi MIURA

IPC分类号： H03M7/30

摘要： According to one embodiment, a data compression device includes a dictionary match determination unit, an extended matching generator, a match selector and a match connector. The dictionary match determination unit searches for first past input data matching first new input data. The extended matching generator compares second past input data subsequent to the first past input data with second new input data subsequent to the first new input data. The match selector generates compressed data by replacing a part of the input data with match information output from the dictionary match determination unit or the extended matching generator. The match connector replaces a plurality of match information in the compressed data with single match information.

公开(公告)号：US20220398019A1

公开(公告)日：2022-12-15

申请号：US17686246

申请日：2022-03-03

申请人： KIOXIA CORPORATION

发明人： Youhei FUKAZAWA ,  Sho KODAMA ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Takashi MIURA ,  Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Zheye WANG

IPC分类号： G06F3/06

摘要： A compression device includes an analyzer circuit, a control circuit, a compressor circuit, and a selector circuit. The analyzer circuit is configured to analyze first data that is input thereto and generate one or more parameter values regarding data compression and/or decompression. The control circuit is configured to generate at least one compression mode information indicating whether or not compression is to be performed, based on the one or more parameter values. The compressor circuit is configured to compress the first data into second data according to the compression mode information. The selector circuit is configured to output the first data if not compressed or the second data if the first data is compressed, together with the compression mode information.

公开(公告)号：US20220353519A1

公开(公告)日：2022-11-03

申请号：US17868597

申请日：2022-07-19

申请人： Kioxia Corporation

发明人： Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Takashi MIURA ,  Kohei OIKAWA ,  Sho KODAMA ,  Youhei FUKAZAWA ,  Zheye WANG

IPC分类号： H04N19/423 ,  H04N19/146 ,  H04N19/13

摘要： According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.