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公开(公告)号：US20240031588A1
公开(公告)日：2024-01-25
申请号：US18479521
申请日：2023-10-02
Applicant: KIOXIA CORPORATION
Inventor： Daisuke YASHIMA , Masato SUMIYOSHI , Keiri NAKANISHI , Takashi MIURA , Kohei OIKAWA , Sho KODAMA , Youhei FUKAZAWA , Zheye WANG
IPC: H04N19/423 , H04N19/146 , H04N19/13
CPC classification number: H04N19/423 , H04N19/146 , H04N19/13 , H04N19/184
Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.
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公开(公告)号：US20230006689A1
公开(公告)日：2023-01-05
申请号：US17688368
申请日：2022-03-07
Applicant: Kioxia Corporation
Inventor： Masato SUMIYOSHI , Keiri NAKANISHI , Kohei OIKAWA , Sho KODAMA
Abstract: According to one embodiment, an interleaving unit divides a symbol string into first and second symbols. A first coding unit converts the first symbols to first codewords. A first packet generating unit generates first packets including the first codewords. A first request generating unit generates first packet requests including sizes of variable length packets. A second coding unit converts the second symbols to second codewords. A second packet generating unit generates second packets including the second codewords. A second request generating unit generates second packet requests including sizes of variable length packets. A multiplexer outputs a compressed stream including the first and second variable length packets cut out from the first and second packets.
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公开(公告)号：US20210250043A1
公开(公告)日：2021-08-12
申请号：US17015874
申请日：2020-09-09
Applicant: Kioxia Corporation
Inventor： Kohei OIKAWA , Masato SUMIYOSHI
Abstract: According to one embodiment, a dividing circuit divides a first bit string into second bit strings and outputs the divided second bit strings. The dividing circuit includes first, second, and third blocks. The first block executes first operation for each bit of a third bit string in the first bit string. The first operation is to calculate a head bit of a succeeding symbol when one bit is assumed to be a head of one symbol. The second block executes second operation for each bit of the third bit string for a set number of times. The second operation is to overwrite boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information. The third block divides the third bit string immediately before a second bit indicated by boundary information associated with a first bit of the third bit string.
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公开(公告)号：US20240204796A1
公开(公告)日：2024-06-20
申请号：US18244621
申请日：2023-09-11
Applicant: Kioxia Corporation
Inventor： Sho KODAMA , Masato SUMIYOSHI
IPC: H03M7/40
CPC classification number: H03M7/405 , H03M7/4056
Abstract: According to one embodiment, a code table generation device includes a frequency table generation unit, a frequency sorting unit, and a Huffman tree generation unit. The frequency table generation unit generates a frequency table including entries each including a symbol and a frequency of occurrence, based on a frequency of occurrence for each symbol of input symbols. The frequency sorting unit sorts the entries in the frequency table by frequency of occurrence. The Huffman tree generation unit generates a Huffman tree having leaf nodes by using a queue that includes storage areas in which the sorted entries are respectively stored as the leaf nodes in an initial state, in response to the entries having been sorted.
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公开(公告)号：US20230291418A1
公开(公告)日：2023-09-14
申请号：US17939692
申请日：2022-09-07
Applicant: Kioxia Corporation
Inventor： Masato SUMIYOSHI , Takashi TAKEMOTO , Keiri NAKANISHI
CPC classification number: H03M7/405 , H03M7/6005
Abstract: According to one embodiment, a data decompression device decodes a code included in compressed data into a symbol. The data decompression device includes a first code length generation unit and a second code length generation unit. The first code length generation unit generates a first code length of a first code included in the compressed data by arithmetic calculation. The second code length generation unit generates a second code length of a second code by using a table. The second code is included in the compressed data. The second code is subsequent to the first code. The table indicates at least the first code and the second code length that is associated with the first code.
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Patent Agency Ranking
公开(公告)号：US20210289217A1
公开(公告)日：2021-09-16
申请号：US17019941
申请日：2020-09-14
Applicant: Kioxia Corporation
Inventor： Daisuke YASHIMA , Masato SUMIYOSHI , Keiri NAKANISHI , Takashi MIURA , Kohei OIKAWA , Sho KODAMA , Youhei FUKAZAWA , Zheye WANG
IPC: H04N19/423 , H04N19/13 , H04N19/146
Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.
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公开(公告)号：US20240223211A1
公开(公告)日：2024-07-04
申请号：US18536057
申请日：2023-12-11
Applicant: Kioxia Corporation
Inventor： Keiri NAKANISHI , Masato SUMIYOSHI , Sho KODAMA
CPC classification number: H03M7/4093 , H03M7/3077 , H03M7/3088 , H03M7/6005 , H03M7/6011 , H03M7/6023
Abstract: According to one embodiment, a conversion device includes a demultiplexer, first to Nth extractors and a deinterleave unit. The demultiplexer extracts first to Nth substreams from a first compressed stream. The first to Nth substreams are placed in order in the first compressed stream and include first variable-length codes to Nth variable-length codes into which first symbols to Nth symbols of a symbol string have been converted. The first to Nth extractors extract the first variable-length codes to the Nth variable-length codes from the first to Nth substreams. The deinterleave unit reorders the first variable-length codes to the Nth variable-length codes in accordance with the symbol string and outputs a second compressed stream.
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公开(公告)号：US20230087517A1
公开(公告)日：2023-03-23
申请号：US17680128
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Kohei OIKAWA , Keiri NAKANISHI , Sho KODAMA , Masato SUMIYOSHI , Daisuke YASHIMA , Youhei FUKAZAWA , Zheye WANG , Takashi MIURA
Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.
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公开(公告)号：US20220255556A1
公开(公告)日：2022-08-11
申请号：US17472431
申请日：2021-09-10
Applicant: Kioxia Corporation
Inventor： Daisuke YASHIMA , Kohei OIKAWA , Sho KODAMA , Keiri NAKANISHI , Masato SUMIYOSHI , Youhei FUKAZAWA , Zheye WANG , Takashi MIURA
Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.
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公开(公告)号：US20220083282A1
公开(公告)日：2022-03-17
申请号：US17191845
申请日：2021-03-04
Applicant: Kioxia Corporation
Inventor： Masato SUMIYOSHI , Keiri NAKANISHI , Sho KODAMA , Kohei OIKAWA
Abstract: A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.
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