公开(公告)号：US11861218B2

公开(公告)日：2024-01-02

申请号：US17981817

申请日：2022-11-07

Applicant: KIOXIA CORPORATION

Inventor： Shinichi Kanno ,  Hideki Yoshida ,  Naoki Esaka ,  Hiroshi Nishimura

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

公开(公告)号：US11321231B2

公开(公告)日：2022-05-03

申请号：US17016666

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Naoki Esaka

IPC: G06F12/02 ,  G06F12/08 ,  G06F13/16 ,  G06F12/0871 ,  G06F13/40 ,  G06F12/0868

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

公开(公告)号：US12079473B2

公开(公告)日：2024-09-03

申请号：US18327108

申请日：2023-06-01

Applicant: KIOXIA CORPORATION

Inventor： Naoki Esaka ,  Shinichi Kanno

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

公开(公告)号：US11836381B2

公开(公告)日：2023-12-05

申请号：US17473634

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Naoki Esaka ,  Shinichi Kanno

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.

公开(公告)号：US11704021B2

公开(公告)日：2023-07-18

申请号：US17536558

申请日：2021-11-29

Applicant: Kioxia Corporation

Inventor： Naoki Esaka ,  Shinichi Kanno

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

公开(公告)号：US11663122B2

公开(公告)日：2023-05-30

申请号：US17699660

申请日：2022-03-21

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Naoki Esaka

IPC: G06F12/02 ,  G06F12/08 ,  G06F13/16 ,  G06F12/0871 ,  G06F13/40 ,  G06F12/0868

CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F12/0871 ,  G06F13/1673 ,  G06F13/4068

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

公开(公告)号：US11216188B2

公开(公告)日：2022-01-04

申请号：US17019955

申请日：2020-09-14

Applicant: Kioxia Corporation

Inventor： Naoki Esaka ,  Shinichi Kanno

IPC: G06F3/06

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

公开(公告)号：US20210149797A1

公开(公告)日：2021-05-20

申请号：US17016666

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Naoki Esaka

IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0868 ,  G06F13/16 ,  G06F13/40

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

公开(公告)号：US11886727B2

公开(公告)日：2024-01-30

申请号：US17653385

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Naoki Esaka

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a controller constructs a plurality of block groups. The plurality of block groups include at least a first block group configured using a first type block group and a second block group configured using a second block group. The first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of a plurality of dies or each of a plurality of planes. The second type block group includes a plurality of non-defective blocks. The number of non-defective blocks included in the second type block group is equal to the number of non-defective blocks included in the first type block.

公开(公告)号：US11726707B2

公开(公告)日：2023-08-15

申请号：US17523415

申请日：2021-11-10

Applicant: KIOXIA CORPORATION

Inventor： Shinichi Kanno ,  Hideki Yoshida ,  Naoki Esaka

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0804

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writ the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.