公开(公告)号：US11543997B2

公开(公告)日：2023-01-03

申请号：US17406619

申请日：2021-08-19

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Hideki Yoshida ,  Naoki Esaka ,  Hiroshi Nishimura

IPC: G06F3/06 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

公开(公告)号：US12229441B2

公开(公告)日：2025-02-18

申请号：US18499750

申请日：2023-11-01

Applicant: KIOXIA CORPORATION

Inventor： Shinichi Kanno ,  Hideki Yoshida ,  Naoki Esaka ,  Hiroshi Nishimura

IPC: G06F3/06 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

公开(公告)号：US11861218B2

公开(公告)日：2024-01-02

申请号：US17981817

申请日：2022-11-07

Applicant: KIOXIA CORPORATION

Inventor： Shinichi Kanno ,  Hideki Yoshida ,  Naoki Esaka ,  Hiroshi Nishimura

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

公开(公告)号：US12131024B2

公开(公告)日：2024-10-29

申请号：US18204854

申请日：2023-06-01

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Hiroshi Nishimura ,  Hideki Yoshida ,  Hiroshi Murayama

IPC: G06F3/06 ,  G06F1/3234 ,  G06F11/10 ,  G06F12/02 ,  G11C16/04 ,  G11C16/24 ,  G11C29/52 ,  H03M13/29

CPC classification number: G06F3/0604 ,  G06F1/3275 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/2906 ,  G06F12/0246 ,  G06F2212/214 ,  G11C16/0483 ,  G11C16/24 ,  Y02D10/00

Abstract: A memory system including: a nonvolatile memory; first and second decoders configured to execute first and second error correction for correcting data read from the nonvolatile memory; and a controller configured to receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command, and after receiving the first command, output data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

公开(公告)号：US11704019B2

公开(公告)日：2023-07-18

申请号：US17078547

申请日：2020-10-23

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno ,  Hiroshi Nishimura ,  Hideki Yoshida ,  Hiroshi Murayama

IPC: G06F3/06 ,  G06F1/3234 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G06F12/02 ,  G11C16/24 ,  G11C16/04

CPC classification number: G06F3/0604 ,  G06F1/3275 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/2906 ,  G06F12/0246 ,  G06F2212/214 ,  G11C16/0483 ,  G11C16/24 ,  Y02D10/00

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.