公开(公告)号：US20240322826A1

公开(公告)日：2024-09-26

申请号：US18677602

申请日：2024-05-29

Applicant: Kioxia Corporation

Inventor： Yasuhiro HIRASHIMA ,  Masaru KOYANAGI ,  Yutaka TAKAYAMA

IPC: H03K19/0175 ,  H01L23/538

CPC classification number: H03K19/017509 ,  H01L23/5384

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

公开(公告)号：US20240321360A1

公开(公告)日：2024-09-26

申请号：US18732188

申请日：2024-06-03

Applicant: Kioxia Corporation

Inventor： Yasuhiro HIRASHIMA ,  Masaru KOYANAGI

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory cell, a detection circuit which detects a first voltage and selects one of a first mode and a second mode based on the first voltage, and a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode. The detection circuit selects the first mode when the first voltage is equal to or greater than a determination value, and selects the second mode when the first voltage is less than the determination value. The transmitting unit outputs the first signal of a first amplitude in the first mode, and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode.

公开(公告)号：US20240321341A1

公开(公告)日：2024-09-26

申请号：US18593233

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Katsuaki SAKURAI ,  Daisuke ARIZONO ,  Mitsuhiro ABE ,  Yasuhiro HIRASHIMA

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

Abstract: A storage device includes a memory cell array, an input/output circuit, and a logic circuit. The input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. The logic circuit is configured to output a first signal to the input/output circuit. The first signal at an active level enables at least a part of the input/output circuit. The logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. The logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. The logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.

公开(公告)号：US20230352093A1

公开(公告)日：2023-11-02

申请号：US18177779

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Yasuhiro HIRASHIMA ,  Toshiyuki KOUCHI

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/32

Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.