公开(公告)号：US20240321341A1

公开(公告)日：2024-09-26

申请号：US18593233

申请日：2024-03-01

申请人： Kioxia Corporation

发明人： Katsuaki SAKURAI ,  Daisuke ARIZONO ,  Mitsuhiro ABE ,  Yasuhiro HIRASHIMA

IPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

CPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

摘要： A storage device includes a memory cell array, an input/output circuit, and a logic circuit. The input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. The logic circuit is configured to output a first signal to the input/output circuit. The first signal at an active level enables at least a part of the input/output circuit. The logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. The logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. The logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.

公开(公告)号：US20220262444A1

公开(公告)日：2022-08-18

申请号：US17463693

申请日：2021-09-01

申请人： Kioxia Corporation

发明人： Ryota HIRAI ,  Daisuke ARIZONO ,  Yasuhiro SHIINO ,  Takuya KUSAKA

IPC分类号： G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/32

摘要： A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value.

公开(公告)号：US20220084595A1

公开(公告)日：2022-03-17

申请号：US17200308

申请日：2021-03-12

申请人： Kioxia Corporation

发明人： Takuya KUSAKA ,  Daisuke ARIZONO ,  Yoshikazu HARADA

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14

摘要： A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

公开(公告)号：US20210065823A1

公开(公告)日：2021-03-04

申请号：US16806684

申请日：2020-03-02

申请人： KIOXIA CORPORATION

发明人： Masato ENDO ,  Daisuke ARIZONO ,  Yoshikazu HARADA

IPC分类号： G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  G11C16/12 ,  G11C16/04

摘要： A semiconductor memory device includes a memory transistor, a word line, a peripheral circuit, and electrodes connected to the peripheral circuit. In response to a write command via the electrodes, the peripheral circuit can execute a first program operation of applying a first program voltage to the word line one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor; and execute a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor. The second program voltage in a k-th second program operation is less than the first program voltage in a k-th first program operation.

公开(公告)号：US20240320089A1

公开(公告)日：2024-09-26

申请号：US18463535

申请日：2023-09-08

申请人： Kioxia Corporation

发明人： Daisuke ARIZONO

IPC分类号： G06F11/10

CPC分类号： G06F11/1044

摘要： According to one embodiment, a memory system includes a nonvolatile memory that includes memory cells. The nonvolatile memory outputs, to a memory controller, first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit, in response to a first command set. The nonvolatile memory outputs, to the memory controller, the first hard bit data, the second hard bit data, the third hard bit data, first soft bit data related to the first bit, second soft bit data related to the second bit, and third soft bit data related to the third bit, in response to a second command set.

公开(公告)号：US20240311294A1

公开(公告)日：2024-09-19

申请号：US18673842

申请日：2024-05-24

申请人： Kioxia Corporation

发明人： Keisuke AZUMA ,  Mitsuaki HONMA ,  Daisuke ARIZONO

IPC分类号： G06F12/02

CPC分类号： G06F12/0246

摘要： According to an embodiment, a memory system includes a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller configured to control the non-volatile memory. The non-volatile memory is configured to output first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit to the memory controller. The memory controller is configured to execute error correction processing using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.

公开(公告)号：US20230170004A1

公开(公告)日：2023-06-01

申请号：US17931945

申请日：2022-09-14

申请人： Kioxia Corporation

发明人： Keisuke AZUMA ,  Mitsuaki HONMA ,  Daisuke ARIZONO

IPC分类号： G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/12

摘要： According to an embodiment, a memory system comprising: a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit and a second bit, and configured to calculate third soft bit data based on a logical sum calculation using at least first soft bit data corresponding to the first bit and second soft bit data corresponding to the second bit; and a memory controller configured to restore the first soft bit data and the second soft bit data based on at least first hard bit data corresponding to the first bit, second hard bit data corresponding to the second bit, and the third soft bit data.