公开(公告)号：US20230317179A1

公开(公告)日：2023-10-05

申请号：US17899014

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Mitsuhiro ABE ,  Yasuhiro HIRASHIMA ,  Mitsuaki HONMA

IPC: G11C16/32 ,  H01L25/065

CPC classification number: G11C16/32 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

公开(公告)号：US20220230665A1

公开(公告)日：2022-07-21

申请号：US17716295

申请日：2022-04-08

Applicant: Kioxia Corporation

Inventor： Yasuhiro HIRASHIMA ,  Mitsuhiro ABE ,  Norichika ASAOKA

IPC: G11C7/10 ,  G11C29/12

Abstract: According to one embodiment, a semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first output buffer configured to output a fourth signal based on a signal selected by the first select circuit; a first output pad configured to externally output the fourth signal; and a counter configured to count a number of times the fourth signal is output.

公开(公告)号：US20240321341A1

公开(公告)日：2024-09-26

申请号：US18593233

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Katsuaki SAKURAI ,  Daisuke ARIZONO ,  Mitsuhiro ABE ,  Yasuhiro HIRASHIMA

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

Abstract: A storage device includes a memory cell array, an input/output circuit, and a logic circuit. The input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. The logic circuit is configured to output a first signal to the input/output circuit. The first signal at an active level enables at least a part of the input/output circuit. The logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. The logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. The logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.

公开(公告)号：US20230298641A1

公开(公告)日：2023-09-21

申请号：US17896907

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Shintaro HAYASHI ,  Mitsuhiro ABE ,  Naoaki KANAGAWA

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/222

Abstract: A semiconductor memory device includes a memory cell array, a storing unit that stores data read out from the memory cell array in storage circuits, an output circuit, and a control circuit. In response to a read request, the control circuit adjusts the value of a read pointer of the storing unit, controls the storing unit to sequentially output to the output circuit first and second data stored in first and second storage circuits of the storing unit, respectively, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and controls the output circuit to transmit the first and second data to the memory controller as dummy data, and thereafter to transmit at least third data to the memory controller as read data.

公开(公告)号：US20230282257A1

公开(公告)日：2023-09-07

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa KUROSAWA ,  Akio SUGAHARA ,  Mitsuhiro ABE ,  Hisashi FUJIKAWA ,  Yuji NAGAI ,  Zhao LU

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/20 ,  G11C7/1069

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.