公开(公告)号：US11211130B2

公开(公告)日：2021-12-28

申请号：US16867263

申请日：2020-05-05

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Mikihiko Ito ,  Kei Shiraishi ,  Fumiya Watanabe

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/30 ,  G11C7/10 ,  G11C16/10

Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.

公开(公告)号：US11121710B2

公开(公告)日：2021-09-14

申请号：US17000708

申请日：2020-08-24

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Yutaka Takayama

IPC: G11C7/10 ,  H03K3/00 ,  H03K19/0175 ,  H01L23/538

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.