公开(公告)号：US11450390B2

公开(公告)日：2022-09-20

申请号：US17118703

申请日：2020-12-11

Applicant: Kioxia Corporation

Inventor： Fumiya Watanabe ,  Masaru Koyanagi ,  Yutaka Shimizu ,  Yasuhiro Hirashima ,  Kei Shiraishi ,  Mikihiko Ito

IPC: G11C11/08 ,  G11C16/32 ,  G11C7/10 ,  G11C16/10

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

公开(公告)号：US11270981B2

公开(公告)日：2022-03-08

申请号：US17023617

申请日：2020-09-17

Applicant: KIOXIA CORPORATION

Inventor： Mikihiko Ito ,  Masaru Koyanagi ,  Masafumi Nakatani ,  Shinya Okuno ,  Shigeki Nagasaka ,  Masahiro Yoshihara ,  Akira Umezawa ,  Satoshi Tsukiyama ,  Kazushige Kawasaki

IPC: G11C16/30 ,  H01L25/065 ,  G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  G11C16/26 ,  H01L27/10 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

公开(公告)号：US11211130B2

公开(公告)日：2021-12-28

申请号：US16867263

申请日：2020-05-05

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Mikihiko Ito ,  Kei Shiraishi ,  Fumiya Watanabe

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/30 ,  G11C7/10 ,  G11C16/10

Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.