公开(公告)号：US12028068B2

公开(公告)日：2024-07-02

申请号：US18178038

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Fumiya Watanabe ,  Toshifumi Watanabe ,  Kazuhiko Satou ,  Shouichi Ozaki ,  Kenro Kubota ,  Atsuko Saeki ,  Ryota Tsuchiya ,  Harumi Abe

IPC: H03K3/011 ,  G11C7/10 ,  H03K17/14 ,  H03K19/20

CPC classification number: H03K3/011 ,  G11C7/1048 ,  H03K17/14 ,  G11C2207/2254 ,  H03K19/20

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

公开(公告)号：US11450390B2

公开(公告)日：2022-09-20

申请号：US17118703

申请日：2020-12-11

Applicant: Kioxia Corporation

Inventor： Fumiya Watanabe ,  Masaru Koyanagi ,  Yutaka Shimizu ,  Yasuhiro Hirashima ,  Kei Shiraishi ,  Mikihiko Ito

IPC: G11C11/08 ,  G11C16/32 ,  G11C7/10 ,  G11C16/10

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

公开(公告)号：US11211130B2

公开(公告)日：2021-12-28

申请号：US16867263

申请日：2020-05-05

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Mikihiko Ito ,  Kei Shiraishi ,  Fumiya Watanabe

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/30 ,  G11C7/10 ,  G11C16/10

Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.

公开(公告)号：US11177008B2

公开(公告)日：2021-11-16

申请号：US16895689

申请日：2020-06-08

Applicant: KIOXIA CORPORATION

Inventor： Kensuke Yamamoto ,  Fumiya Watanabe ,  Shouichi Ozaki

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/32 ,  G11C7/10 ,  G06F3/06 ,  H03K5/156 ,  G11C29/50

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.