Automation and platform management system for naval vessels
    11.
    发明授权
    Automation and platform management system for naval vessels 失效
    海军舰艇自动化与平台管理系统

    公开(公告)号:US07099755B2

    公开(公告)日:2006-08-29

    申请号:US10448225

    申请日:2003-05-30

    Abstract: An automation and platform management system for navel vessels configured to be operated from a multimedia information and operation control center. This automation and management system has a system for monitoring and commanding the ship, a system for navigating the ship, a system for coordinating weapons deployment, a system for handling the external and internal radio communications, a system for controlling and handling the information distribution, a system for power generation and distribution (power management monitoring), and a system for monitoring ship operations. To be able further to reduce the number of crewmembers of a ship equipped with the automation and management system, the automation and management system further has a system for automated ship damage control and/or an integrated onboard information and data network (2) and/or an integrated system for monitoring and control of a COPAW drive of the ship.

    Abstract translation: 一种用于脐带血管的自动化和平台管理系统,其配置为从多媒体信息和操作控制中心操作。 该自动化管理系统具有船舶监视和指挥系统,船舶导航系统,协调武器部署系统,处理外部和内部无线电通信的系统,控制和处理信息分发的系统, 发电和配电系统(电力管理监控)以及船舶运行监控系统。 为了进一步减少配备有自动化和管理系统的船员人数,自动化和管理系统还具有用于自动船舶损坏控制和/或集成的车载信息和数据网络(2)和/ 或用于监测和控制COPAW驾驶船舶的综合系统。

    Method and apparatus for changing the imaging scale in X-ray lithograph
    12.
    发明授权
    Method and apparatus for changing the imaging scale in X-ray lithograph 失效
    用于改变X射线平版印刷术中成像尺度的方法和装置

    公开(公告)号:US4887282A

    公开(公告)日:1989-12-12

    申请号:US119094

    申请日:1987-11-10

    CPC classification number: G03F7/702 G03F7/70783

    Abstract: Am improved method for changing the image scale for a lithographic arrangement comprising a synchroton radiation creating a collimated beam of x-radiation passing through a mask onto an object to be structured, characterized by deforming the surface to be structured into a curved surface. The deforming into a curved surface can be either into a cylindrical curved surface or into a spherical curved surface.

    Abstract translation: 用于改变用于光刻装置的图像尺度的改进方法包括同步辐射,该同步辐射产生通过掩模穿过掩模的准直的x射线束到待构造的物体上,其特征在于使被构造成曲面的表面变形。 变形为弯曲表面的形状可以是圆柱形曲面或球形曲面。

    Apparatus for the exact mutual alignment of a mask and semiconductor
wafer in a lithographic apparatus
    13.
    发明授权
    Apparatus for the exact mutual alignment of a mask and semiconductor wafer in a lithographic apparatus 失效
    用于光刻设备中掩模和半导体晶片的精确相互对准的装置

    公开(公告)号:US4825086A

    公开(公告)日:1989-04-25

    申请号:US73760

    申请日:1987-07-15

    CPC classification number: G03F7/70691 G03F9/70

    Abstract: An arrangement and method for the exact, mutual alignment of a mask and a semiconductor wafer in a lithographic apparatus so that the mask and wafer are in a plane extending perpendicular to the particle beam. The apparatus includes a seating arrangement for the mask having a first retaining part and arrangement for positioning this first retaining part relative to a table which allows adjusting the plane of the first retaining part. The apparatus also includes a second retaining part for securing the wafer thereto, which second retaining part is mounted on the plate by an arrangement that allows adjusting the plane of the second retaining part relative to the axis so that the surface of the semiconductor wafer can also be placed in a plane extending perpendicular to the beam direction.

    Abstract translation: 一种用于光刻设备中的掩模和半导体晶片的精确的相互对准的布置和方法,使得掩模和晶片处于垂直于粒子束延伸的平面中。 该装置包括用于掩模的座位装置,其具有第一保持部分和用于将该第一保持部分相对于允许调节第一保持部分的平面的工作台定位的装置。 该设备还包括用于将晶片固定到其上的第二保持部件,该第二保持部件通过允许相对于轴线调整第二保持部件的平面的布置而安装在板上,使得半导体晶片的表面也可以 放置在垂直于光束方向延伸的平面内。

    Semiconductor devices and methods of manufacture thereof
    14.
    发明授权
    Semiconductor devices and methods of manufacture thereof 有权
    半导体器件及其制造方法

    公开(公告)号:US08603918B2

    公开(公告)日:2013-12-10

    申请号:US13091612

    申请日:2011-04-21

    CPC classification number: H01L21/743

    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.

    Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中,半导体器件包括具有设置在其顶部下方的掩埋层的工件。 沟槽设置在至少延伸穿过掩埋层的工件中。 至少一个沉降片触点设置在工件的顶部。 所述至少一个沉降片接触件邻近所述沟槽的至少一部分的侧壁并且与所述掩埋层相邻。 绝缘材料设置在沟槽的侧壁上。 导电材料设置在沟槽内并联接到工件的下部。

    Method for the production of an anti-reflecting surface on optical integrated circuits
    15.
    发明授权
    Method for the production of an anti-reflecting surface on optical integrated circuits 有权
    在光学集成电路上制造抗反射表面的方法

    公开(公告)号:US07736927B2

    公开(公告)日:2010-06-15

    申请号:US11408618

    申请日:2006-04-21

    CPC classification number: H01L31/1804 H01L31/02363 Y02E10/547 Y02P70/521

    Abstract: A photodetector is formed in a semiconductor body. A hard mask grating is photolithographically formed on a surface of the semiconductor body. The semiconductor body is etched using the hard mask grating as a mask. The etching is performed down to a predetermined depth. An implantation is performed such that an anode or cathode of the photodetector that has been interrupted during the etching is re-formed.

    Abstract translation: 光电检测器形成在半导体本体中。 在半导体本体的表面上光刻地形成硬掩模光栅。 使用硬掩模光栅作为掩模蚀刻半导体本体。 蚀刻到达预定深度。 进行注入,使得在蚀刻期间被中断的光电检测器的阳极或阴极被重新形成。

    APPARATUS INCORPORATING AN ELECTRONIC DISPLAY
    16.
    发明申请
    APPARATUS INCORPORATING AN ELECTRONIC DISPLAY 审中-公开
    装置电子显示器的装置

    公开(公告)号:US20100123644A1

    公开(公告)日:2010-05-20

    申请号:US12327544

    申请日:2008-12-03

    CPC classification number: G09F9/35 G09F9/00

    Abstract: Apparatus comprises an electronic display, a processor coupled to the electronic display and configured by software to divide the electronic display into first and second display portions, a frame member including at least two surround members and a divider member. The frame member is secured adjacent the electronic display so that the surround members provide a surround to at least two opposite edges of the electronic display and such that the first display portion of the electronic display is on an opposite side of the divider member to the second display portion of the electronic display, and wherein the processor is configured by software to control the display to provide a first image in the first display portion and a second image in the second display portion, the second image being independent of the first image.

    Abstract translation: 装置包括电子显示器,耦合到电子显示器并由软件配置的处理器,用于将电子显示器分成第一和第二显示部分,框架构件包括至少两个环绕构件和分隔构件。 框架构件被固定在电子显示器附近,使得环绕构件为电子显示器的至少两个相对边缘提供环绕,并且使得电子显示器的第一显示部分在分隔构件的相对侧到第二 电子显示器的显示部分,并且其中处理器由软件配置以控制显示器以在第一显示部分中提供第一图像,并且在第二显示部分中提供第二图像,第二图像独立于第一图像。

    Semiconductor Devices and Methods of Manufacture Thereof
    17.
    发明申请
    Semiconductor Devices and Methods of Manufacture Thereof 有权
    半导体器件及其制造方法

    公开(公告)号:US20090243041A1

    公开(公告)日:2009-10-01

    申请号:US12060626

    申请日:2008-04-01

    CPC classification number: H01L21/743

    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.

    Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中,半导体器件包括具有设置在其顶部下方的掩埋层的工件。 沟槽设置在至少延伸穿过掩埋层的工件中。 至少一个沉降片触点设置在工件的顶部。 所述至少一个沉降片接触件邻近所述沟槽的至少一部分的侧壁并且与所述掩埋层相邻。 绝缘材料设置在沟槽的侧壁上。 导电材料设置在沟槽内并联接到工件的下部。

    Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor
    18.
    发明申请
    Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor 有权
    用于制造具有双极晶体管和异质双极晶体管的集成电路和集成电路的方法

    公开(公告)号:US20050156193A1

    公开(公告)日:2005-07-21

    申请号:US10987952

    申请日:2004-11-12

    CPC classification number: H01L21/8249 H01L21/8222 H01L27/0623 H01L27/0825

    Abstract: For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.

    Abstract translation: 为了将npn双极晶体管与异质双极晶体管集成,在构造用于两种类型的晶体管的集电极结构之后,在异质双极晶体管的基极区域中产生占位符层,其中占位符层不存在于基极区域 的双极晶体管。 在产生双极晶体管的基极之后,双极晶体管的基极被覆盖,于是除去占位符层,并且在占位符层被去除的位置产生异质双极晶体管的基极。 对于两种类型的晶体管,再次产生发射极结构,使得集成电路的结果包括双极晶体管和异质双极晶体管,其集电极结构和/或其发射极结构由相同的生产层组成。 因此,可以利用两种类型的晶体管的优点来产生节省空间和成本有效的集成电路。

    Device for detecting transmission errors in balanced two-wire bus lines
and two-bus interfaces
    19.
    发明授权
    Device for detecting transmission errors in balanced two-wire bus lines and two-bus interfaces 失效
    用于检测平衡双线总线和双总线接口传输误差的装置

    公开(公告)号:US5483639A

    公开(公告)日:1996-01-09

    申请号:US212885

    申请日:1994-03-14

    CPC classification number: H04L1/24

    Abstract: A device for monitoring balanced two-wire bus lines and two-wire but interfaces has first, second and third comparison circuits for comparing the wire potentials with one another and with a fixed reference voltage, and two shift registers or counters as well as at least one pulse generator for deriving reset pulses from each change in sign of the potential comparison of the two bus conductors with one another. The shift registers or counters are respectively reset by the reset pulses. Result signals produced from the comparison of the bus potentials with a fixed reference voltage can be fed to the shift registers or counters for the purpose of shifting or incrementing said registers or counters respectively. The register length or number of counter stages can be selected as a function of a desired bit error tolerance depth. The device can be extended by a self-resetting system after temporary bus disturbances. The device is also programmable, and thereby universal, and because of an integration capability using standard technology and having a very low space requirement is suitable as a compilable standard cell for possible bus chip designs. The device is operable in cooperation with software routines of a decentral bus test system as a test receiver for analyzing bus disturbances.

    Abstract translation: 用于监控平衡的双线总线和两线但接口的装置具有用于比较线电位彼此和固定参考电压的第一,第二和第三比较电路,以及至少两个移位寄存器或计数器 一个脉冲发生器,用于从两个总线导体彼此的电位比较的符号的每个改变中导出复位脉冲。 移位寄存器或计数器分别由复位脉冲复位。 可以将总线电位与固定参考电压的比较产生的结果信号分别馈送到移位寄存器或计数器,以分别移位或递增所述寄存器或计数器。 寄存器长度或计数器级数可以根据所需的位误差公差深度来选择。 临时总线扰动后,可通过自复位系统扩展该设备。 该器件也是可编程的,从而是通用的,并且由于使用标准技术并具有非常低的空间要求的集成能力作为可用的总线芯片设计的可编译标准单元是合适的。 该设备可与作为用于分析总线扰动的测试接收机的分散总线测试系统的软件程序协同工作。

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