公开(公告)号：US20190131175A1

公开(公告)日：2019-05-02

申请号：US15797302

申请日：2017-10-30

申请人： Avago Technologies General IP (Singapore) Pte. Ltd

发明人： Thomas Edward Dungan ,  Jonathan Kwadwo Abrokwah ,  Forest Dixon ,  William Snodgrass

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/8249 ,  H01L21/823481 ,  H01L21/8252 ,  H01L23/562 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/0825 ,  H01L29/0813 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/66666 ,  H01L29/7322 ,  H01L29/7827

摘要： A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alterative stress path that substantially bypasses the transistor.

公开(公告)号：US09692405B2

公开(公告)日：2017-06-27

申请号：US15348350

申请日：2016-11-10

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Hyoungjun Na ,  Ken Toshiyuki ,  Shouji Abou

IPC分类号： H03K5/08 ,  H03K17/06 ,  H03K17/567 ,  H01L27/06 ,  H01L29/739 ,  H01L29/861 ,  H01L49/02 ,  H01L23/528 ,  H01L29/73

CPC分类号： H03K17/06 ,  H01L23/528 ,  H01L27/0635 ,  H01L27/0825 ,  H01L28/20 ,  H01L29/73 ,  H01L29/7393 ,  H01L29/861 ,  H03K17/127 ,  H03K17/567 ,  H03K2217/94042

摘要： A switching circuit switches a first IGBT and a second IGBT. A control circuit is equipped with a first switching element that is configured to be able to control a gate current of the first IGBT, a second switching element that is configured to be able to control a gate current of the second IGBT, and a third switching element that is connected between an electrode of the first IGBT and an electrode of the second IGBT. The control circuit controls a turn on timing and turn off timing.

公开(公告)号：US08901669B2

公开(公告)日：2014-12-02

申请号：US13560517

申请日：2012-07-27

申请人： Hans Mertens ,  Johannes Theodorus Marinus Donkers ,  Evelyne Gridelet ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee

发明人： Hans Mertens ,  Johannes Theodorus Marinus Donkers ,  Evelyne Gridelet ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee

IPC分类号： H01L29/66

CPC分类号： H01L21/8222 ,  H01L21/82285 ,  H01L27/0825 ,  H01L27/0826

摘要： A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.

摘要翻译： 一种制造集成电路的方法，包括包括第一和第二类型双极晶体管的双极晶体管，所述方法包括提供包括第一隔离区域的衬底，每个隔离区域与第二隔离区域分离，所述有源区域包括所述双极晶体管之一的集电极杂质; 在衬底上形成基层堆叠; 在所述第一类型双极晶体管的区域中在所述基极层堆叠上形成第一有效厚度的第一发射极盖层; 在所述第二类型双极晶体管的区域中形成与所述基极层叠层上的所述第一有效厚度不同的第二有效厚度的第二发射极帽层; 以及在每个双极晶体管的发射极盖层上形成发射极。 根据这种方法的IC。

公开(公告)号：US08648391B2

公开(公告)日：2014-02-11

申请号：US13429262

申请日：2012-03-23

申请人： Jeffrey A. Babcock ,  Alexei Sadovnikov

发明人： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC分类号： H01L29/66

CPC分类号： H01L29/66242 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/7371

摘要： The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.

摘要翻译： SiGe异质结双极晶体管（HBT）的击穿电压（BVCEO）和截止频率（fT）的乘积通过利用具有从基极向下延伸的中空芯的掺杂区域而增加到约翰逊极限以上， 掺杂的埋地集电区。 掺杂区域和掩埋集电极区域具有相反的掺杂剂类型。

公开(公告)号：US20130071994A1

公开(公告)日：2013-03-21

申请号：US13539339

申请日：2012-06-30

申请人： Hideaki Tsuchiko

发明人： Hideaki Tsuchiko

IPC分类号： H01L21/265

CPC分类号： H01L21/74 ,  H01L21/2253 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/0821 ,  H01L27/0825 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0821 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/8611

摘要： The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance.

公开(公告)号：US07939420B2

公开(公告)日：2011-05-10

申请号：US12070036

申请日：2008-02-14

申请人： Donald R. Disney ,  Richard K. Williams

发明人： Donald R. Disney ,  Richard K. Williams

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L21/761 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

摘要： Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

摘要翻译： 用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。 一个过程将沟槽对准地板隔离区域。 在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20100109118A1

公开(公告)日：2010-05-06

申请号：US12603592

申请日：2009-10-22

申请人： MASATO SAKURAI ,  AKIHIRO SAWAIRI

发明人： MASATO SAKURAI ,  AKIHIRO SAWAIRI

IPC分类号： H01L27/06

CPC分类号： H01L29/7322 ,  H01L27/0825 ,  H01L29/0821

摘要： A semiconductor device of the present invention includes a semiconductor layer, a low withstand voltage transistor, and a high withstand voltage transistor. In the low withstand voltage transistor, a first high concentration collector region and a first base region contact with a first low concentration collector region provided in the semiconductor layer. In the high withstand voltage transistor, a second high concentration collector region and a second base region contact a second low concentration collector region provided in the semiconductor layer. Further, the second high concentration collector region and the second base region are configured such that the distance between the second high concentration collector region and the second base region in a parallel direction to a main surface of the semiconductor layer is longer than the distance between the first high concentration collector region and the first base region.

摘要翻译： 本发明的半导体器件包括半导体层，低耐压晶体管和高耐压晶体管。 在低耐压晶体管中，第一高浓度集电极区域和第一基极区域与设置在半导体层中的第一低浓度集电极区域接触。 在高耐压晶体管中，第二高浓度集电极区域和第二基极区域接触设置在半导体层中的第二低浓度集电极区域。 此外，第二高浓度集电极区域和第二基极区域被构造成使得第二高浓度集电极区域和第二基极区域在与半导体层的主表面平行的方向上的距离比第二高浓度集电极区域和第二基极区域之间的距离长 第一高浓度集电区和第一碱区。

公开(公告)号：US07679223B2

公开(公告)日：2010-03-16

申请号：US11412338

申请日：2006-04-27

申请人： Anant K. Agarwal ,  Sumithra Krishnaswami ,  James T. Richmond, Jr.

发明人： Anant K. Agarwal ,  Sumithra Krishnaswami ,  James T. Richmond, Jr.

IPC分类号： H01H47/24

CPC分类号： H01L29/66068 ,  H01L21/8213 ,  H01L27/0825 ,  H01L29/1608 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/11 ,  H01L31/1113 ,  H01L31/167 ,  H03K17/615 ,  H03K17/79 ,  H03K17/7955 ,  Y10T307/773

摘要： An electronic circuit includes a primary wide bandgap bipolar power switching device configured to supply a load current in response to a control signal applied to a control terminal thereof, and a driver device configured to generate the control signal. At least one of the primary switching device or the driver device may include an optically triggered switching device. A discrete wide bandgap semiconductor device includes a primary bipolar device stage configured to switch between a conducting state and a nonconducting state upon application of a control current, and a bipolar driver stage configured to generate the control current and to supply the control current to the primary bipolar device stage. At least one of the primary bipolar device stage and the bipolar driver stage may include an optically triggered wide bandgap switching device.

摘要翻译： 电子电路包括主宽带隙双极型功率开关装置，其被配置为响应于施加到其控制端的控制信号而提供负载电流;以及驱动器装置，被配置为产生控制信号。 主开关装置或驱动器装置中的至少一个可以包括光学触发的开关装置。 分立的宽带隙半导体器件包括主要双极器件级，其被配置为在施加控制电流时在导通状态和非导通状态之间切换;双极性驱动器级，被配置为产生控制电流并将控制电流提供给初级 双极器件阶段。 主要双极器件级和双极驱动器级中的至少一个可以包括光学触发的宽带隙开关器件。

公开(公告)号：US07550787B2

公开(公告)日：2009-06-23

申请号：US10908884

申请日：2005-05-31

申请人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

发明人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

IPC分类号： H01L29/737

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

公开(公告)号：US20080227261A1

公开(公告)日：2008-09-18

申请号：US12051928

申请日：2008-03-20

申请人： Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

发明人： Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

IPC分类号： H01L21/331

CPC分类号： H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

摘要： The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths.The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages.

摘要翻译： 本发明涉及一种用于制造晶体管结构的方法，该方法至少包括具有不同集电极宽度的第一和第二双极晶体管。 本发明的区别在于，不同掺杂区域之间的所有结点都具有尖锐的界面。 在这种情况下，作为示例，第一集电极区域2.1适用于具有高限制频率f T T的高频晶体管，并且第二集电极区域2.2适用于具有 增加击穿电压。