公开(公告)号：USRE33738E

公开(公告)日：1991-11-12

申请号：US828081

申请日：1986-02-07

申请人： Takatoshi Okumura

发明人： Takatoshi Okumura

IPC分类号： G10H1/08 ,  G10H7/06

CPC分类号： G10H7/06 ,  G10H1/08 ,  G10H2250/545

摘要： An electronic musical instrument includes a plurality of address generators for producing address signals corresponding to different tones each varying at a rate synchronous with the frequency of each of the different tones, a waveform memory device including a plurality of addresses for storing at respective addresses a plurality of waveform sample values that constitute a waveform, a circuit for sequentially supplying one after another of the address signals to the waveform memory device to read out the waveform in different rates in a time division multiplexed manner for different tones, and musical tone forming circuits for forming musical tones in accordance with the time division multiplexed waveform outputs of the waveform memory device.

公开(公告)号：US4897636A

公开(公告)日：1990-01-30

申请号：US139170

申请日：1987-12-21

申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

IPC分类号： G06T1/60 ,  G09G5/02 ,  G09G5/393

CPC分类号： G09G5/393 ,  G06T1/60 ,  G09G5/026

摘要： A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area. A reading circuit reads the display data in the first memory locations in accordance with the first address data, while a writing circuit writes the read display data into the second memory locations in accordance with the second address data. This video display control system further includes another reading circuit and an operation circuit. This reading circuit reads the display data in the second memory locations and feeds the read display data to the operation circuit which effects an operation such as a logical operation or a transparency processing on each pair of the display data read from the first and second memory locations.

摘要翻译： 视频显示控制系统能够将静止图像的一部分从第一显示区域移动到屏幕上的第二显示区域。 视频显示控制系统包括由多个存储位置组成的存储器，用于存储表示屏幕上显示元素的图像的多个显示数据。 第一和第二寄存器保持表示第一和第二显示区域的第一和第二区域数据，并且地址数据生成器从这些区域数据生成第一和第二地址数据，第一地址数据指示存储对应于第一和第二显示区域的显示数据的存储单元 显示区域，第二地址数据指示存储对应于第二显示区域的显示数据的第二存储单元。 读取电路根据第一地址数据读取第一存储器位置中的显示数据，而写入电路根据第二地址数据将读取的显示数据写入第二存储器位置。 该视频显示控制系统还包括另一读取电路和操作电路。 该读取电路读取第二存储器位置中的显示数据并将读取的显示数据馈送到对从第一和第二存储器位置读取的每对显示数据执行诸如逻辑操作或透明度处理的操作的操作电路 。

公开(公告)号：US4731742A

公开(公告)日：1988-03-15

申请号：US712253

申请日：1985-03-15

申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

IPC分类号： G09G5/02 ,  G09G5/393 ,  G06F3/153

CPC分类号： G09G5/393 ,  G09G5/02

摘要： A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM. Through this second register, the memory accessing circuit performs a memory accessing operation such as a transfer of color code between the external device and the VRAM, whereby color painting on a display area such as a rectangular area, dot and a line can easily be achieved. The VDP further comprises an operation circuit for effecting a certain operation on a color code in the second register and a color code in the VRAM and generating a new color code in accordance with the operation result. The operation-related color change on a display area can be achieved by storing the new color code in a corresponding memory location of the VRAM.

摘要翻译： 一种用于在视频显示单元的屏幕上显示视频图像的视频显示控制系统。 该视频显示控制系统基本上包括VRAM（视频RAM）和视频显示处理器（VDP）。 VRAM具有与屏幕上的显示元素相对应的存储器位置。 VDP包括用于接收区域信息的第一寄存器，用于识别屏幕上的显示区域;地址发生器，用于根据区域信息产生对应于显示区域的存储位置的地址;以及存储器访问电路，用于访问具有 地址。 因此，通过该VDP的存储器访问操作不需要中央处理单元的复杂支持。 VDP还包括用于存储从外部设备提供或从VRAM读取的颜色代码的第二寄存器。 通过该第二寄存器，存储器访问电路执行存储器访问操作，例如外部设备和VRAM之间的颜色代码的传送，由此可以容易地实现诸如矩形区域，点和行的显示区域上的彩色绘画 。 VDP还包括用于对第二寄存器中的颜色代码进行某种操作的操作电路和VRAM中的颜色代码，并根据操作结果生成新的颜色代码。 可以通过将新的颜色代码存储在VRAM的对应的存储器位置中来实现显示区域上的与操作相关的颜色变化。

公开(公告)号：US4442748A

公开(公告)日：1984-04-17

申请号：US390830

申请日：1982-06-22

申请人： Makoto Kaneko ,  Takatoshi Okumura

发明人： Makoto Kaneko ,  Takatoshi Okumura

IPC分类号： G10H5/00 ,  G10H5/06 ,  H03K23/64 ,  G10H1/00

CPC分类号： H03K21/38 ,  G10H5/06 ,  Y10S84/11

摘要： A frequency divider which divides clock pulses to obtain the clock frequency of a desired dividing ratio comprises a binary counter, cycle data forming circuit and inhibit circuit to which the dividing ratio is fed in the form of the dividing ratio data.The counter counts the clock pulses, and the cycle data forming circuit converts the count value of the binary counter to a cycle data in which a certain single bit only becomes a logical state "1" and the rest of the bits are a state "0". The bit which becomes "1" in the cycle data is uniquely determined by the count value. Further, each bit of the cycle data becomes "1" in proportion to the weight of the each bit. With the cycle data being thus formed, the dividing ratio data is simplified.The inhibit circuit receives the cycle data and the dividing ratio data to suspend the counting operation of the binary count if the bit of the dividing ratio data corresponding to the bit of the cycle data whose state is "1" is also "1". This suspension enables the binary counter to perform a nonbinary counting operation, whereby the frequency-dividing based on the desired dividing ratio in the binary counter is implemented. By relating the diving ratio data to the pitch of a note, the frequency divider may be applicable to an electronic musical instrument.

摘要翻译： 划分时钟脉冲以获得期望分频比的时钟频率的分频器包括以分频比数据的形式馈送分频比的二进制计数器，周期数据形成电路和禁止电路。 计数器对时钟脉冲进行计数，周期数据形成电路将二进制计数器的计数值转换为某个单个位仅为逻辑状态“1”的周期数据，其余位为状态“0” “。 循环数据中变为“1”的位由计数值唯一确定。 此外，周期数据的每个比特与每个比特的权重成比例地变为“1”。 随着周期数据的形成，分割比数据被简化。 如果与状态为“1”的循环数据的位对应的分频比数据的位也为“1”，则禁止电路接收周期数据和分频比数据以暂停二进制计数的计数操作。 该暂停使得二进制计数器能够执行非二进制计数操作，由此实现基于二进制计数器中的期望分频比的分频。 通过将潜水比数据与笔记的间距相关联，分频器可以应用于电子乐器。

公开(公告)号：US4217804A

公开(公告)日：1980-08-19

申请号：US952098

申请日：1978-10-17

申请人： Eiichi Yamaga ,  Akira Nakada ,  Takatoshi Okumura ,  Eiichiro Aoki ,  Akiyoshi Oya ,  Yasuji Uchiyama

发明人： Eiichi Yamaga ,  Akira Nakada ,  Takatoshi Okumura ,  Eiichiro Aoki ,  Akiyoshi Oya ,  Yasuji Uchiyama

IPC分类号： G10H1/28 ,  G10H1/42 ,  G10H1/38

CPC分类号： G10H1/28 ,  G10H1/42 ,  Y10S84/12 ,  Y10S84/22

摘要： An electronic musical instrument having a channel processor. The channel processor includes a tone production assignment circuit and an automatic arpeggio circuit. The tone production assignment circuit includes a key code memory circuit of a plurality of channels and an assignment control unit. A specific channel among the channels is used exclusively for the automatic arpeggio performance while the other channels are used for ordinary respective tone production corresponding to depressed keys by an ordinary key assignment operation responsive to depression of the keys. The automatic arpeggio circuit produces key codes one after another for the automatic arpeggio channel in accordance with the key codes already assigned to the respective ordinary channels and with arpeggio constituent orders in a sounding pattern. The arpeggio sounding pattern which is selected in response to a rhythm to be played contains binary data representing the arpeggio constituent orders. The arpeggio constituent orders herein mean the orders of the locations of the notes constituting the arpeggio alignment, the order being counted from the lowest one of the depressed keys in a predetermined keyboard range.

摘要翻译： 一种具有通道处理器的电子乐器。 频道处理器包括音调制作分配电路和自动琶音电路。 音调制作分配电路包括多个通道的键码存储电路和分配控制单元。 信道之中的特定频道专用于自动琶音性能，而其他频道用于通过响应于按键的普通键分配操作而对应于按下的按键的普通相应乐音。 自动琶音电路根据已经分配给各个普通通道的键代码和探测模式中的琶音分量命令一个接一个地产生用于自动琶音通道的键码。 响应于要播放的节奏选择的琶音探测模式包含表示琶音分量的二进制数据。 这里的琶音构成命令是指构成琶音对准的音符的位置的顺序，该顺序从预定的键盘范围中的最低的一个按下的键计数。

公开(公告)号：US4131049A

公开(公告)日：1978-12-26

申请号：US729690

申请日：1976-10-05

申请人： Takatoshi Okumura ,  Shimaji Okamoto

发明人： Takatoshi Okumura ,  Shimaji Okamoto

IPC分类号： G10H1/08 ,  G10H7/00 ,  G10H7/10 ,  G10H1/00

CPC分类号： G10H7/105

摘要： A plurality of waveshape memories are provided for storing the sampled values of one cycle sinusoidal wave as the fundamental frequency, two cycle sinusoidal wave as the second harmonic, . . . and m cycle sinusoidal wave as the m-th harmonic and, in addition thereto, of harmonic-abundant complex waves such as a triangular wave, a sawtooth wave and a rectangular wave. These waveshape memories are read at the same reading rate. The read out sinusoidal waves and triangular, sawtooth and rectangular waves are controlled in their relative levels in accordance with the tone-color of an intended musical tone wave shape. The sinusoidal waves and the triangular, sawtooth and rectangular waves are thereafter synthesized to produce a desired tone-color wave shape. Since the triangular, sawtooth and rectangular waves contain abundant harmonic components, many kinds of musical tones containing abundant harmonic components can be produced despite a limited number of waveform memories.

摘要翻译： 提供了多个波形存储器，用于存储作为基频的一个周期正弦波的采样值，作为二次谐波的两个周期的正弦波。 。 。 并且将周期正弦波作为m次谐波，并且除此之外还包括诸如三角波，锯齿波和矩形波之类的谐波丰富的复数波。 这些波形存储器以相同的读取速率读取。 读出的正弦波和三角形，锯齿波和矩形波根据预期乐音波形的色调被控制在它们的相对电平。 此后，合成正弦波和三角形，锯齿波和矩形波以产生所需的色调波形。 由于三角形，锯齿波和矩形波都包含丰富的谐波分量，尽管波形存储器数量有限，但是可以产生包含丰富的谐波分量的多种音调。

公开(公告)号：US4026180A

公开(公告)日：1977-05-31

申请号：US581181

申请日：1975-05-27

申请人： Norio Tomisawa ,  Yasuji Uchiyama ,  Takatoshi Okumura ,  Toshio Takeda

发明人： Norio Tomisawa ,  Yasuji Uchiyama ,  Takatoshi Okumura ,  Toshio Takeda

IPC分类号： G10H1/043

CPC分类号： G10H1/043

摘要： In a digital type electronic musical instrument in which basic frequency information corresponding to a depressed key is cumulatively counted and a musical tone waveshape is read from a memory by the resultant output of the cumulative counting, a musical tone including a coarse noise is produced by randomly frequency-modulating the basic frequency of the musical tone, thereby providing the tone with a random vibrato effect. The frequency-modulation is effected by randomly adding or subtracting information expressed in the form of a certain frequency difference relative to the basic frequency information to or from the basic frequency information. According to an embodiment of the invention, a noise effect is produced only during a rise portion of the musical tone by reducing noise component in steps from the start of depression of a key and reproducing a musical tone of a normal pitch after a lapse of a predetermined period of time. The degree of the noise effect can be controlled for each individual keyboard.

摘要翻译： 在通过累积计数的合成输出累积计数与按下的键对应的基本频率信息并从存储器中读出乐音波形的数字式电子乐器中，通过随机地产生包括粗噪声的乐音 对音调的基本频率进行频率调制，从而提供具有随机颤音效果的音调。 通过以相对于基本频率信息为基准频率信息的特定频率差异的形式表示的信息，从基本频率信息中随机增加或减去信息来实现频率调制。 根据本发明的一个实施例，噪声效应仅在音乐的上升部分期间通过从键的开始逐步减小噪声分量并在经过一个音调之后再现正常音调的乐音而产生 预定时间段。 可以对每个单独的键盘控制噪音效果的程度。

公开(公告)号：US5444687A

公开(公告)日：1995-08-22

申请号：US36437

申请日：1993-03-24

申请人： Takatoshi Okumura

发明人： Takatoshi Okumura

IPC分类号： G11B7/00 ,  G11B7/0045 ,  G11B7/005 ,  G11B7/085 ,  G11B7/125 ,  G11B11/105 ,  G11B19/28 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B27/10

CPC分类号： G11B7/126 ,  G11B19/28 ,  G11B20/10 ,  G11B27/105 ,  G11B7/0045 ,  G11B7/005 ,  G11B7/085 ,  G11B11/10595 ,  G11B20/1258 ,  G11B20/1403

摘要： In a method and a device for accessing an optical disc such as a Compact Disc, a CD-ROM, a CD-I and a MD, an optical disc in which data is recorded or to be recorded at a constant linear velocity is rotated at a substantially constant number of revolution per unit time and this optical disc is accessed on the basis of a clock signal which changes its frequency in accordance with an access position (i.e., a read position or write position). Since random accessing is made in a state in which the optical disc is rotated at a substantially constant number of revolution per unit time, it is not necessary to wait in accessing until a stable revolution number is attained but the waiting time is determined only by time required for moving of the read head. This enables the waiting time to be reduced and thereby realizes accessing to the optical disc at a higher speed.

摘要翻译： 在用于访问诸如光盘，CD-ROM，CD-I和MD的光盘的方法和装置中，以恒定线速度记录数据或以恒定线速度记录的光盘被旋转 基于每单位时间基本上恒定的转数，并且该光盘是基于根据访问位置（即，读取位置或写入位置）改变其频率的时钟信号来访问的。 由于在光盘以每单位时间大致恒定的转数旋转的状态下进行随机访问，因此不需要等待访问直到获得稳定的转数，而是仅通过时间确定等待时间 移动读取头所需的。 这使得能够降低等待时间，从而以更高的速度实现对光盘的访问。

公开(公告)号：US5416497A

公开(公告)日：1995-05-16

申请号：US943706

申请日：1992-09-11

申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura

发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura

IPC分类号： G09G5/06 ,  G09G5/42 ,  G09G5/02 ,  G09G5/22 ,  G09G5/34

CPC分类号： G09G5/42 ,  G09G5/06

摘要： A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result. When the animation patterns overlaps, the VDP can also deliver a collision signal in place of the logical operation, thereby enabling a CPU to recognize the position of the overlapping portion.

摘要翻译： 视频显示控制系统在视频显示单元的屏幕上显示多色动画图案。 视频显示控制系统主要由视频RAM（VRAM）和视频显示处理器（VDP）构成。 VRAM存储动画图案数据，显示位置数据和至少两个颜色数据。 VDP读取这些数据，并使屏幕上的显示位置以至少两种颜色显示动画图案图像。 动画图案图像，两种颜色和显示位置由动画图案数据，两种颜色数据和显示位置数据确定。 在另一个视频显示控制系统中，VRAM存储至少两组动画图案数据，显示位置数据和颜色数据。 当显示两个动画图案时，VDP相对于两个图案的重叠部分对两个颜色数据进行逻辑运算，并使得重叠部分以对应于操作结果的新颜色显示。 当动画图案重叠时，VDP也可以传递碰撞信号代替逻辑操作，从而使CPU能够识别重叠部分的位置。

公开(公告)号：US4812828A

公开(公告)日：1989-03-14

申请号：US106007

申请日：1987-10-07

申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura

发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura

IPC分类号： G06F3/153 ,  G06F3/033 ,  G06F3/038 ,  G09G5/00 ,  G09G1/16

CPC分类号： G06F3/038

摘要： A video display processor (VDP) is connectable to an input control device such as a light pen and a mouse. The VDP comprises a counter circuit which is composed of an X counter and a Y counter. When a mouse mode is selected, X and Y pulse signals are supplied to the X and Y counters so that the contents of the X and Y counters represent the amount of movement of the mouse. When a central processing unit (CPU) connected to the VDP reads the contents of the X and Y counters in this mouse mode, the X and Y counters are reset. When a light pen mode is selected, the X and Y counters effect a count operation of a clock signal generated in the VDP in synchronism with the display of image on a screen so that the contents of the X and Y counters represents X-Y coordinates of a display element which is currently displayed on the screen. The CPU reads the contents of the X and Y counters in response to a light detection signal outputted from the light pen thereby to input the X-Y coordinates of the display element selected by the light pen. In a collision detection mode, the counter circuit effects the same counting operation as that effected in the light pen mode. The CPU reads the contents of the X and Y counters in response to a collision detection signal, which is generated by an associated circuit when animation patterns of the video image displayed on the screen overlap, thereby to input the X-Y coordinates of the collision position.

摘要翻译： 视频显示处理器（VDP）可连接到诸如光笔和鼠标之类的输入控制装置。 VDP包括由X计数器和Y计数器组成的计数器电路。 当选择鼠标模式时，X和Y脉冲信号被提供给X和Y计数器，使得X和Y计数器的内容表示鼠标的移动量。 当连接到VDP的中央处理单元（CPU）在该鼠标模式下读取X和Y计数器的内容时​​，X和Y计数器被复位。 当选择光笔模式时，X和Y计数器与屏幕上的图像的显示同步地影响在VDP中产生的时钟信号的计数操作，使得X和Y计数器的内容表示XY坐标 当前显示在屏幕上的显示元素。 CPU响应于从光笔输出的光检测信号读取X和Y计数器的内容，从而输入由光笔选择的显示元件的X-Y坐标。 在碰撞检测模式中，计数器电路实现与在光笔模式中实现的相同的计数操作。 响应于在屏幕上显示的视频图像的动画图案重叠时由相关联的电路产生的冲突检测信号，CPU读取X和Y计数器的内容，从而输入碰撞位置的X-Y坐标。