公开(公告)号：US5485457A

公开(公告)日：1996-01-16

申请号：US319039

申请日：1994-10-06

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04L12/937 ,  H04L12/939 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/552 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/565 ,  H04L49/15 ,  H04L49/254

摘要： In a packet switching system having input ports (20-1-1 to 20-8-8) supplied with input packets and output ports (21-1-1 to 21-8-8) producing output packets, each of time stampers (22-1-1 to 22-8-8) connected to the input ports assigns a time stamp to the input packet supplied thereto to produce a time stamped packet. Connected to the time stampers, each of primary switches (23-1 to 23-8) carries out a primary switching operation on the time stamped packets supplied thereto so as to connect input lines thereof and output lines thereof in one-to-one correspondence to produce primary switched packets. Connected to the primary switches in a cross link connection fashion, each of secondary switches (24-1 to 24-8) carries out a secondary switching operation on the primary switched packets on the basis of destination addresses thereof in sequence to produce secondary switched packets. Connected to the secondary switches in the cross link connection fashion, each of tertiary switches (25-1 to 25-8) corrects sequence of the secondary switched packets on the basis of the time stamps assigned thereto to produce sequence corrected packets and then carries out a tertiary switching operation on the sequence corrected packets on the basis of the destination addresses thereof to produce tertiary switched packets. Each output port produces each tertiary switched packet as each output port.

摘要翻译： 在具有供给输入分组的输入端口（20-1-1至20-8-8）和产生输出分组的输出端口（21-1-1至21-8-8）的分组交换系统中，每个时间戳 22-1-1至22-8-8）向输入端口分配一个时间戳，以产生一个时间戳分组。 连接到时间戳的每个主开关（23-1至23-8）对提供给它的时间戳包进行初次切换操作，以便将其输入线和其输出线一一对应 以产生主交换分组。 以交叉连接方式连接到主交换机，每个辅助交换机（24-1至24-8）依次以其目的地地址对主交换分组进行二次交换操作，以产生二次交换分组 。 以交叉连接方式连接到次级交换机，三级交换机（25-1至25-8）中的每一个根据分配给其的时间戳来校正二次交换分组的序列，以产生序列校正分组，然后执行 基于其目的地地址对序列校正的分组进行三次切换操作，以产生三次切换分组。 每个输出端口产生每个三次交换分组作为每个输出端口。

公开(公告)号：US06373845B1

公开(公告)日：2002-04-16

申请号：US09133406

申请日：1998-08-13

申请人： Toshiya Aramaki ,  Yasuhiro Miyao

发明人： Toshiya Aramaki ,  Yasuhiro Miyao

IPC分类号： H04L1228

CPC分类号： H04L49/3009 ,  H04L49/253 ,  H04L49/30 ,  H04L49/602

摘要： A multilayer ATM communication equipment includes a port VPI-VCI table, an ATM switch, an MAC frame forming section, a flow VPI-VCI table, a flow identification section, a port MAC address table, and an MAC switch section. The port VPI-VCI table stores transfer route information and input/output port information. The ATM switch transfers the ATM cell from the output port corresponding to the output port information on the basis of the transfer route information and the input port number. The MAC frame forming section forms an MAC frame on the basis of the transfer route information. The flow VPI-VCI table stores flow information and transfer output information. The flow identification section transfers the MAC frame on the basis of the transfer output information. The port MAC address table stores the destination information of the MAC frame and transfer output information. When transfer output information is stored in the port MAC address table, the MAC switch section transfers the MAC frame on the basis of the transfer output information. Otherwise, the MAC switch section assigns a new input port, notifies a transmission-side switch of the flow information and the input port, sets a shortcut path, and transfers the MAC frame from the notified output port.

摘要翻译： 多层ATM通信设备包括端口VPI-VCI表，ATM交换机，MAC帧形成部分，流VPI-VCI表，流标识部分，端口MAC地址表和MAC切换部分。 端口VPI-VCI表存储传输路由信息和输入/输出端口信息。 ATM交换机根据传输路由信息和输入端口号，从对应于输出端口信息的输出端口传送ATM信元。 MAC帧形成部分基于传送路径信息形成MAC帧。 流VPI-VCI表存储流信息和传输输出信息。 流识别部分基于传送输出信息传送MAC帧。 端口MAC地址表存储MAC帧的目的地信息和传送输出信息。 当传送输出信息存储在端口MAC地址表中时，MAC切换部分根据传送输出信息传送MAC帧。 否则，MAC交换机分配一个新的输入端口，通知发送方交换机的流量信息和输入端口，设置快捷路径，并从通知的输出端口传送MAC帧。

公开(公告)号：US5864553A

公开(公告)日：1999-01-26

申请号：US780468

申请日：1997-01-08

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04Q3/00 ,  H04L12/931 ,  H04L12/951 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L49/102 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/351

摘要： A multiport frame exchange system is disclosed having a plurality of input and output lines and which outputs frame data inputted from these input and output lines to desired input and output lines based on frame header information. This multiport frame exchange system is composed of input frame buffers provided for each input line that store inputted frames; output frame buffers provided for each output line that store and output output frames; a header processor that processes the headers of frames; and a self-routing section that connects the input frame buffers, the output frame buffers, and the header processor.

摘要翻译： 公开了具有多个输入和输出线的多端口帧交换系统，并且基于帧头信息将从这些输入和输出线输入的帧数据输出到期望的输入和输出线。 该多端口帧交换系统由为存储输入帧的每个输入线提供的输入帧缓冲器组成; 为存储和输出输出帧的每条输出行提供的输出帧缓冲区; 处理帧的头部的头处理器; 以及连接输入帧缓冲器，输出帧缓冲器和头处理器的自路由部分。

公开(公告)号：US5402417A

公开(公告)日：1995-03-28

申请号：US198266

申请日：1994-02-18

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04L12/70 ,  H04L12/953 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04Q11/0478 ,  H04L49/1507 ,  H04L49/3018 ,  H04L49/3027

摘要： A packet switching system includes a plurality of incoming channels, through which packets arrive. The system has a circuit providing arrival time information for header information of respective packets. The arrival time information is then copied by a copying circuit. The copied information is accumulated in an arrival time information accumulating circuit in an order of the arrival time. On the other hand, the packet is accumulated by a packet accumulating circuit in an order of the arrival time. A control circuit is adapted to output the packets accumulated in the packet accumulating circuit and having the arrival time information consistent with the arrival time information accumulated at the leading end of the arrival time information accumulating circuit. The packets are output from the packet accumulating circuit according to destinations contained in the header information thereof through a plurality of outgoing channels for feeding out the routed packets.

摘要翻译： 分组交换系统包括分组到达的多个输入信道。 该系统具有提供相应分组的报头信息的到达时间信息的电路。 然后通过复印电路复印到达时间信息。 复制信息以到达时间的顺序累积在到达时间信息累积电路中。 另一方面，分组由分组累积电路以到达时间的顺序累积。 控制电路适于输出累积在分组累积电路中的分组，并且具有与到达时间信息累加电路的前端累积的到达时间信息一致的到达时间信息。 根据包含在其标题信息中的目的，通过用于馈送路由分组的多个输出信道，从分组累积电路输出分组。