公开(公告)号：USRE37959E1

公开(公告)日：2003-01-07

申请号：US09160791

申请日：1998-09-25

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Hitoshi Kume ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Hitoshi Kume ,  Hideaki Yamamoto

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

摘要： An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded. The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.

摘要翻译： EEPROM（电可擦除可编程只读存储器）具有其源极区域附近的每个存储单元MISFET的浮置栅电极的角部为圆形的结构。EEPROM通过以下方法制造，其特征在于，杂质的离子 以高剂量注入与存储单元MISFET的浮置栅极电极和控制栅电极自对准，以形成其源极和漏极区域，由此进行氧化处理。

公开(公告)号：US06451643B2

公开(公告)日：2002-09-17

申请号：US09873451

申请日：2001-06-05

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L218238

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.

摘要翻译： 一种制造具有非易失性存储单元的半导体存储器件的方法，每个半导体存储器单元均由具有浮置栅极和控制栅极以及第一和第二半导体区域的MISFET构成。 通过该方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是，在第二半导体区域的形成中引入较低剂量的砷。 第一半导体区域形成为具有大于第二半导体区域的结深度的结深度，并且第一和第二半导体区域都具有在浮栅电极下延伸的部分。 存储在浮置栅电极中的载体通过隧穿穿过浮栅电极下方的绝缘膜而在浮置栅极电极和第一半导体区域之间传输。 该方法还特征在于外围电路的MISFET的形成。

公开(公告)号：US5904518A

公开(公告)日：1999-05-18

申请号：US885184

申请日：1997-06-30

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886 ,  G11C16/0416 ,  H01L27/0688

摘要： A method of manufacturing a semiconductor memory device having nonvolatile memory cells of a single-element type. The method provides for the formation of a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. Also by this method, an impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region, for example, during an erase operation of the memory, by tunneling through the insulating film beneath the floating gate electrode. The method also calls for the formation of MISFETs associated with peripheral circuitry of the memory.

摘要翻译： 一种制造具有单一元件类型的非易失性存储单元的半导体存储器件的方法。 该方法提供了通过第二栅极绝缘膜在浮栅上隔离地形成半导体衬底的主表面上的浮栅电极和控制栅电极。 此外，通过该方法，与控制栅电极的一对相对端侧自对准地引入杂质，例如砷，以形成第一和第二半导体区域，但是较低剂量的砷为 引入第二半导体区域的形成。 根据该方案，第一半导体区域形成为具有大于与第二半导体区域相关联的结深度的结深度，并且第一和第二半导体区域都具有在浮置栅极下方延伸的部分。 此外，例如在存储器的擦除操作期间，存储在浮置栅电极中的载流子通过隧穿穿过浮置栅电极下方的绝缘膜而被转移到第一半导体区域。 该方法还要求形成与存储器的外围电路相关联的MISFET。

公开(公告)号：US5656839A

公开(公告)日：1997-08-12

申请号：US422941

申请日：1995-04-17

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886 ,  G11C16/0416 ,  H01L27/0688

摘要： A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

摘要翻译： 在具有场效应晶体管的非易失性存储器电路中具有非易失性存储元件或单元型存储单元的半导体集成器件，除了用于存储信息的浮栅电极和控制栅极之外， 电极，其包括具有从其主表面延伸的半导体衬底的深度的重掺杂区域。 此外，单元件型场效应晶体管具有漏极，其包括从其主表面延伸到半导体衬底中的深度较小的轻掺杂区域。

公开(公告)号：US5472891A

公开(公告)日：1995-12-05

申请号：US260229

申请日：1994-06-14

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukuda ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukuda ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/266 ,  H01L21/8247

CPC分类号： H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并且采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5155701A

公开(公告)日：1992-10-13

申请号：US535298

申请日：1990-06-08

申请人： Kazuhiro Komori ,  Yuji Hara ,  Hideaki Takahashi ,  Minoru Fukuda ,  Satoshi Meguro

发明人： Kazuhiro Komori ,  Yuji Hara ,  Hideaki Takahashi ,  Minoru Fukuda ,  Satoshi Meguro

IPC分类号： G11C29/50

CPC分类号： G11C29/50016 ,  G11C29/50 ,  G11C16/04

摘要： An EPROM and a method of testing the former, in which a defective memory cell caused by defects in the insulating films between a substrate and a floating gate and between the floating gate and a control gate can be tested without writing any data in the individual memory cells by holding data lines to a low potential and word lines fed with a voltage.

摘要翻译： EPROM和测试前者的方法，其中可以测试由衬底和浮动栅极之间以及浮置栅极和控制栅极之间的绝缘膜中的缺陷引起的有缺陷的存储器单元，而不在单个存储器中写入任何数据 通过将数据线保持为低电位并且馈送有电压的字线。

公开(公告)号：US4818716A

公开(公告)日：1989-04-04

申请号：US111690

申请日：1987-10-22

申请人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

发明人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/265 ,  B01J17/00

CPC分类号： H01L27/1126

摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

摘要翻译： 公开了具有串联连接的多个MISFET的垂直型只读存储器（ROM）的存储单元。 MISFET包括形成有多个导电层的栅电极，其中一些MISFET被设置为耗尽型，并且至少一些剩余的MISFET被设置为增强型，以便将信息写入存储单元。 信息写入操作通过至少两个步骤进行。 也就是说，在第一信息写入步骤中，使用栅电极作为掩模来注入杂质; 并且在第二步骤中，通过栅电极将杂质注入到半导体衬底的表面中。 这些步骤使得能够生产半导体存储器件，例如具有降低的串联电阻并且适于高度集成的存储单元的垂直型掩模ROM。 此外，公开了一种半导体存储器件的存储结构，其适用于通过多层栅电极的布置而具有更高的集成度。

公开(公告)号：US07399667B2

公开(公告)日：2008-07-15

申请号：US11393774

申请日：2006-03-31

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

摘要翻译： 一种具有非易失性存储单元的半导体存储器单元，每个非易失性存储单元分别由具有浮置栅极和控制栅极的MISFET形成，以及用作源极和漏极区域的第一和第二半导体区域。 根据其制造方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是具有较低剂量的第二半导体区域，使得形成的第一半导体区域达到结深度 大于第二半导体区域，并且第一和第二半导体区域都具有在浮置栅电极下方延伸的部分。 该装置及其方法的特征还在于外围电路的MISFET的形成。

公开(公告)号：US20060172482A1

公开(公告)日：2006-08-03

申请号：US11393774

申请日：2006-03-31

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

公开(公告)号：US07071050B2

公开(公告)日：2006-07-04

申请号：US11220723

申请日：2005-09-08

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.