公开(公告)号：US06195305B1

公开(公告)日：2001-02-27

申请号：US09288512

申请日：1999-04-08

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

公开(公告)号：US5854562A

公开(公告)日：1998-12-29

申请号：US842536

申请日：1997-04-15

申请人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

发明人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

公开(公告)号：US06385118B2

公开(公告)日：2002-05-07

申请号：US09907929

申请日：2001-07-19

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

公开(公告)号：US06046609A

公开(公告)日：2000-04-04

申请号：US188369

申请日：1998-11-10

申请人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

发明人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。

公开(公告)号：US5963483A

公开(公告)日：1999-10-05

申请号：US133952

申请日：1998-08-14

申请人： Hideharu Yahata ,  Kenichi Fukui ,  Yoji Nishio ,  Atsushi Hiraishi ,  Sadayuki Morita

发明人： Hideharu Yahata ,  Kenichi Fukui ,  Yoji Nishio ,  Atsushi Hiraishi ,  Sadayuki Morita

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.

摘要翻译： 一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器 锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。 还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器 来自选择器的数据信号根据时钟信号。 输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。 输出缓冲器从输出锁存器接收并输出放大的输出数据信号。 每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持 并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。

公开(公告)号：US5936909A

公开(公告)日：1999-08-10

申请号：US13911

申请日：1998-01-27

申请人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

发明人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

IPC分类号： G11C7/10 ,  G11C11/418 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C11/418 ,  G11C7/1018

摘要： A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

摘要翻译： 静态RAM具有多个存储器堆，每个存储器堆包括在多个字线和多个数据线之间的交点处以矩阵模式形成的多个静态存储器单元。 地址选择电路在接收到地址寄存器中的地址信号后，选择存储器垫之一中的存储单元，并将所选择的存储单元连接到与所讨论的存储器衬垫对应的读出放大器或写入放大器。 同时，地址计数器产生与已经选择了一个存储器垫的地址信号对应的地址信号。 当通过控制信号指定突发模式时，允许进入地址寄存器的地址信号用于选择第一存储器存储器中的存储器单元。 所选择的存储单元连接到相应的读出放大器或写放大器。 然后根据地址计数器产生的地址信号，选择另一个存储器存储器中的存储单元并将其连接到相应的读出放大器或写入放大器。