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公开(公告)号：US06385118B2
公开(公告)日：2002-05-07
申请号：US09907929
申请日：2001-07-19
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
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公开(公告)号：US06195305B1
公开(公告)日：2001-02-27
申请号：US09288512
申请日：1999-04-08
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
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公开(公告)号：US06584031B2
公开(公告)日：2003-06-24
申请号：US10107139
申请日：2002-03-28
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
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公开(公告)号：US06288967B1
公开(公告)日：2001-09-11
申请号：US09742078
申请日：2000-12-22
IPC分类号： G11C700
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
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5.发明授权Method of manufacturing a semiconductor integrated circuit device having a capacitor 失效具有电容器的半导体集成电路器件的制造方法
公开(公告)号：US5976929A
公开(公告)日：1999-11-02
申请号：US962878
申请日：1997-11-03
IPC分类号： H01L27/105 , H01L27/108 , H01L21/8242
CPC分类号： H01L27/105 , H01L27/10805
摘要： A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.
摘要翻译： 一种具有由存储单元组成的DRAM的半导体集成电路器件，包括： 沉积在半导体衬底的主表面上并用于形成存储器单元选择MISFET的栅电极的第一导电膜; 沉积在第一导电膜上并用于形成位线以将存储器单元的数据传送到读出放大器的第二导电膜; 沉积在所述第二导电膜上并用于形成电容器的存储节点的第三导电膜; 沉积在所述第三导电膜上并用于形成所述电容器的平板电极的第四导电膜; 以及沉积在第四导电膜上并用于形成互连的第五导电膜，其中布置在存储器阵列附近的直接外围电路中的晶体管通过由第三导电膜形成的焊盘层电连接到互连 所述第五导电膜沉积在所述第四导电膜上，从而允许形成在所述焊盘层上的所述接触孔的纵横比减小。
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6.发明授权
公开(公告)号：US5604365A
公开(公告)日：1997-02-18
申请号：US297039
申请日：1994-08-29
IPC分类号： H01L27/105 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/105 , H01L27/10805
摘要： A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.
摘要翻译： 一种具有由存储单元组成的DRAM的半导体集成电路器件，包括： 沉积在半导体衬底的主表面上并用于形成存储器单元选择MISFET的栅电极的第一导电膜; 沉积在第一导电膜上并用于形成位线以将存储器单元的数据传送到读出放大器的第二导电膜; 沉积在所述第二导电膜上并用于形成电容器的存储节点的第三导电膜; 沉积在所述第三导电膜上并用于形成所述电容器的平板电极的第四导电膜; 以及沉积在第四导电膜上并用于形成互连的第五导电膜，其中布置在存储器阵列附近的直接外围电路中的晶体管通过由第三导电膜形成的焊盘层电连接到互连 所述第五导电膜沉积在所述第四导电膜上，从而允许形成在所述焊盘层上的所述接触孔的纵横比减小。
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公开(公告)号：US07492341B2
公开(公告)日：2009-02-17
申请号：US10895884
申请日：2004-07-22
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3677
摘要： A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
摘要翻译： 提供了通过集成半导体电路并实现芯片尺寸减小而获得的缩小电路规模的半导体电路和半导体集成电路芯片。 为此，使用双解码方法。 该方法使用：预解码电路，包括前级的第一解码器，其对八位地址信号的任意位进行解码，以及解码剩余位的前一级的第二解码器; 电平转换电路，其使预解码电路的输出移位; 以及后解码电路，其解码通过电平转换电路进行电平转换的预解码电路中的解码器的解码输出。
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公开(公告)号：US06934210B2
公开(公告)日：2005-08-23
申请号：US10190480
申请日：2002-07-09
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/409 , G11C29/08 , G11C7/00 , G11C7/04
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
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公开(公告)号：US07292496B2
公开(公告)日：2007-11-06
申请号：US11472252
申请日：2006-06-22
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。
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公开(公告)号：US20060227091A1
公开(公告)日：2006-10-12
申请号：US11395177
申请日：2006-04-03
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/3614 , G09G3/3648 , G09G3/3696 , G09G2300/0408 , G09G2310/0289 , G09G2310/0297 , G09G2320/0209
摘要： A semiconductor integrated circuit for driving a liquid crystal display, capable of improving the quality of an image displayed by preventing an imbalance between the outputs of a pair of amplifiers for positive voltage and negative voltage for AC driving of the liquid crystal panel and transmission of noise from one amplifier to the other amplifier is realized. A driver circuit that generates and outputs dive signals to be applied to signal lines of the liquid crystal panel includes decoder circuits, each of which selects a gray-scale voltage corresponding to image data. It also includes amplifiers for positive voltage which perform impedance conversion of positive voltages selected by the decoder circuits and amplifiers for negative voltage which perform impedance conversion of negative voltages selected by the decoder circuits. Furthermore, it includes an AC output section consisting of switch circuits, each of which alternately conducts an output of each amplifier for positive voltage to one of two adjacent output terminals and an output of each amplifier for negative voltage to the other one of the two adjacent terminals and vice versa. Two pairs of supply voltages having the same potential difference are generated as supply voltages to the amplifiers for positive voltage and the amplifiers for negative voltage and supplied through separate power supply lines.
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