公开(公告)号：US07058118B1

公开(公告)日：2006-06-06

申请号：US09831829

申请日：1999-11-25

申请人： Akihiro Horii ,  Kenichi Shiraishi

发明人： Akihiro Horii ,  Kenichi Shiraishi

IPC分类号： H03B13/00 ,  H04L27/06

CPC分类号： H04H40/90 ,  H04L1/0039 ,  H04L1/0041 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/0072 ,  H04L1/0075 ,  H04L1/0079 ,  H04L2001/0093

摘要： A demodulator having an improved reliability of the decoding of a TMCC signal is used for digital broadcasting receivers for receiving digital broadcasting by layered transmission system. A pseudo-pattern generator (8) generates fixed pseudo-data which involves no error with respect to a main signal after a TMCC signal and maintains the convolution relationship, and inserts the pseudo-data between the TMCC signal and the main signal through a selector (6B) and a selector (6), thereby conducting Viterbi decoding.

摘要翻译： 具有改进的TMCC信号解码可靠性的解调器被用于通过分层传输系统接收数字广播的数字广播接收机。 伪图案生成器（8）生成固定的伪数据，其对于TMCC信号之后的主信号没有错误，并维持卷积关系，并且通过选择器在TMCC信号和主信号之间插入伪数据 （6B）和选择器（6），从而进行维特比解码。

公开(公告)号：US06748037B1

公开(公告)日：2004-06-08

申请号：US09554690

申请日：2000-05-18

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matuda

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matuda

IPC分类号： H04L2706

CPC分类号： H04L27/2273 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0077 ,  H04L2027/0095

摘要： A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit (6) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit (92) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit (94) calculates the polarity of the error frequency. A step frequency control circuit (96) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.

摘要翻译： 提供一种数字广播接收机，其可以快速地再现载波并以高速捕获期望的信号。 载波再现相位误差检测电路（6）根据在标题部分中的预定部分期间解调调制波的解调波得到的解调输出来检测相位误差电压。 峰值计算电路（92）根据相位误差电压计算期望的接收频率和再现载波频率之间的误差频率。 差分系数计算电路（94）计算误差频率的极性。 步进频率控制电路（96）将计算出的极性的计算误差频率转换为用于自动频率控制的步进频率宽度。 以转换的步进频率宽度扫描再现载波频率，直到在检测到帧同步之后建立帧同步。 因此，可以快速地再现载体并以高速捕获期望的信号。

公开(公告)号：US06693978B1

公开(公告)日：2004-02-17

申请号：US09424832

申请日：1999-12-01

申请人： Akihiro Horii ,  Kenichi Shiraishi

发明人： Akihiro Horii ,  Kenichi Shiraishi

IPC分类号： H04L2714

CPC分类号： H04L27/2273 ,  H03J2200/02 ,  H04L1/206

摘要： A carrier reproducing circuit capable of reproducing a carrier quickly, wherein: a signal point arrangement converting circuit (14) detects the signal point arrangement of a demodulating baseband signal of a carrier when the carrier has a frequency different by a predetermined value from the center frequency of the modulated wave; a variance calculating circuit (15) calculates, based on the signal point arrangement, the number of times that the variance exceeds a preset threshold per unit time; a CN determination circuit (16) determines the reception CN ratio based on the number of times; a scanning step frequency width converting circuit (19) sets a frequency width changed by one step based on the determined reception CN ratio; the carrier for demodulating is sent out by changing oscillation frequencies of oscillators (6, 7) through an AFC circuit (20) based on the present frequency width; and when a carrier synchronization judging circuit (18) detects that the number of times decreases to a value equal to or smaller than a threshold determined based on the reception CN ratio, the scanning by the AFC circuit (20) is stopped.

摘要翻译： 一种能够快速再现载波的载波再现电路，其中：当载波具有与中心频率不同的预定值的频率时，信号点排列转换电路（14）检测载波的解调基带信号的信号点排列 的调制波; 方差计算电路（15）基于信号点排列计算每单位时间的方差超过预设阈值的次数; CN确定电路（16）基于次数确定接收CN比; 扫描步长频率变换电路（19）基于所确定的接收CN比设定改变了一步的频率宽度; 通过基于当前频率宽度通过AFC电路（20）改变振荡器（6,7）的振荡频率来发送用于解调的载波; 并且当载波同步判断电路（18）检测到次数减少到等于或小于基于接收CN比确定的阈值的值时，由AFC电路（20）的扫描停止。

公开(公告)号：US06678336B1

公开(公告)日：2004-01-13

申请号：US09554669

申请日：2000-08-09

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H04L2706

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0081 ,  H04L2027/0095

摘要： A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.

摘要翻译： 一种能够通过根据接收C / N值设置解调操作来稳定同步捕获和稳定解调的分级发送数字解调器。 CNR测量电路从运算电路接收解调输出并测量接收C / N值。 在捕获同步之前的一段时间内，根据解调输出再现载波，以便在报头部分中的调制波和突发符号信号的调制波。 在捕获同步之后，以中间C / N值，根据标题部分的解调输出，突发符号信号和QPSK信号，并根据逻辑门电路的输出，以及在高和低C / N值通过根据来自逻辑门​​电路的信号设置增益控制电路的载波再生环路增益来重放载波。

公开(公告)号：US07529321B1

公开(公告)日：2009-05-05

申请号：US09805766

申请日：1999-09-17

申请人： Kenichi Shiraishi ,  Shoichi Suzuki ,  Akihiro Horii ,  Shoji Matsuda ,  Takahiro Wada

发明人： Kenichi Shiraishi ,  Shoichi Suzuki ,  Akihiro Horii ,  Shoji Matsuda ,  Takahiro Wada

IPC分类号： H04L27/22

CPC分类号： H04H20/74 ,  H04L1/20 ,  H04L27/2273 ,  H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0081

摘要： A digital satellite broadcast receiver capable of an optimum signal reception even when an arbitrary outdoor unit is connected. Please noise characteristics of an outdoor unit connected to a digital satellite broadcast receiver when receiving a burst symbol is estimated based on a bit error rate of an 8PSK modulation signal determined by a trellis decoder (7) when a CNR measured by a CNR measurement circuit (5) is equal to a preset value, and, based on the estimated phase noise characteristics of the outdoor unit, a filter factor of a loop filter (9) inserted into a carrier regenerative loop is set.

摘要翻译： 即使连接任意的室外机也能够进行最佳的信号接收的数字卫星广播接收机。 当接收到突发符号时，连接到数字卫星广播接收机的室外单元的噪声特性基于由CNR测量电路（CNR）测量的CNR由网格解码器（7）确定的8PSK调制信号的误比特率 5）等于预设值，并且基于所估计的室外单元的相位噪声特性，设置插入到载波再生回路中的环路滤波器（9）的滤波器因子。

公开(公告)号：US07283569B2

公开(公告)日：2007-10-16

申请号：US10168148

申请日：2000-12-19

申请人： Hiroshi Okamura ,  Tomokazu Nakajima ,  Takanori Fujii ,  Susumu Nishijima ,  Masaki Miyamoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Hiroshi Okamura ,  Tomokazu Nakajima ,  Takanori Fujii ,  Susumu Nishijima ,  Masaki Miyamoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H04J3/06

CPC分类号： H04L1/06 ,  H04B7/18523 ,  H04B7/18534 ,  H04B7/2125 ,  H04H20/26 ,  H04H20/74

摘要： A site diversity method, a digital satellite broadcast receiving method and a digital satellite broadcast receiver are provided which can make a difference of data output timing between a main station and a subsidiary station at the time of site exchange as small as possible and can perform re-synchronization as soon as possible. In the site diversity method for digital satellite broadcast, when a site exchange execution designation signal is received, the site is exchanged during a period of a TMCC information field of a predetermined specific frame of a super frame determined when the execution designation signal is received. On the receiver side, information of broadcast is continuously received by detecting a TMCC information field in a specific frame during a period of which field the site was exchanged and by establishing re-synchronization by using a super frame sync pattern W2 or W3 after the detected TMCC information field.

摘要翻译： 提供一种站点分集方法，数字卫星广播接收方法和数字卫星广播接收机，其可以在站点交换时使主站和辅助站之间的数据输出定时的差异尽可能小，并且可以执行re - 尽快同步。 在数字卫星广播的站点分集方法中，当接收到站点交换执行指定信号时，在接收到执行指定信号时确定的超帧的预定特定帧的TMCC信息字段的周期期间交换站点。 在接收机侧，通过在交换场所的时段期间检测特定帧中的TMCC信息字段并且通过使用超帧同步模式W 2或W 3之后建立再同步来连续接收广播信息 检测到的TMCC信息字段。

公开(公告)号：US07260158B2

公开(公告)日：2007-08-21

申请号：US10398943

申请日：2001-09-25

申请人： Kenichi Shiraishi ,  Akihiro Horii

发明人： Kenichi Shiraishi ,  Akihiro Horii

IPC分类号： H03K9/00 ,  H04L27/06 ,  H04L27/14 ,  H04L27/22

CPC分类号： H04H60/32 ,  H04H60/12 ,  H04N21/434 ,  H04N21/4345 ,  H04N21/4382 ,  H04N21/4621

摘要： A digital broadcast receiver capable of adequately receiving a higher-level layer service along with a lower-level layer service even if the reception CNR degrades. A demodulation decoding section (2) of the receiver judges on the basis of transport and multiplexing configuration control information whether the TS packet allocated to each slot is adapted to a higher-level layer service or a lower-level layer service and informs a code writing section (3) of the result. The code writing section (3) writes, in each TS packet, a layer identification code for judging whether the TS packet is adapted to a higher-level layer service or a lower-layer service and synthesizes a resultant TS packet. A stream separating section (4) reads the layer identification code along with the PID in the packet header included in the TS packet and finds and extracts a desired TS packet.

摘要翻译： 即使接收CNR劣化，能够适当地接收更高级别的层服务以及较低层次的服务的数字广播接收机。 接收机的解调解码部分（2）根据传输和多路复用配置控制信息判断分配给每个时隙的TS分组是否适合于较高级别的层服务或较低层服务，并通知代码写入 第（3）节结果。 代码写入部分（3）在每个TS分组中写入一个层识别码，用于判断TS分组是适应于较高级别的服务还是适用于较低层服务，并且合成所产生的TS分组。 流分离部分（4）在TS分组中包含的分组报头中读取与PID一起的层识别码，并发现并提取期望的TS分组。

公开(公告)号：US07221719B2

公开(公告)日：2007-05-22

申请号：US10031085

申请日：2001-05-17

申请人： Kenichi Shiraishi ,  Shoji Matsuda ,  Akihiro Horii

发明人： Kenichi Shiraishi ,  Shoji Matsuda ,  Akihiro Horii

IPC分类号： H04L27/14

CPC分类号： H04L27/2273 ,  H04L27/0012 ,  H04L2027/0053 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0069

摘要： An improved apparatus for receiving BS digital broadcast is disclosed. The apparatus for receiving BS digital broadcast of the present invention has first to third filters and a selective complex calculator circuit.Each of the first to third filters 18 to 20 identifies the modulation technique applied to the received signal, by the modulation identification signals A0, A1 received from a timing generator circuit 25, and filters a phase error signal PED according to the identified modulation technique. The selective complex calculator circuit 21 shifts the phase of a signal point indicated by an I signal ADI1 and a Q signal ADQ1 absolute-phased by an absolute-phasing section 14, by a phase corresponding to the phase error signal filtered by the first to third filters 18 to 20. At this moment, the selective complex calculator circuit 21 selects the phase error signal corresponding to the modulation technique identified from the modulation identification signals A0, A1 received from the timing generator circuit 25. Consequently, in the burst receiving, it is possible to reduce the effect on the error rate because of the signal noise of the ODU to a degree equal to that in the continuous receiving.

摘要翻译： 公开了一种用于接收BS数字广播的改进的装置。 本发明的用于接收BS数字广播的装置具有第一至第三滤波器和选择性复合计算器电路。 第一至第三滤波器18至20中的每一个通过从定时发生器电路25接收的调制识别信号A 0，A 1识别应用于接收信号的调制技术，并根据所识别的调制对相位误差信号PED进行滤波 技术。 选择复合计算器电路21将由由绝对定相部分14绝对相位的I信号ADI 1和Q信号ADQ 1指示的信号点的相位移位相应于由第一 到第三过滤器18至20。 此时，选择性复数计算器电路21选择与从定时发生器电路25接收的调制识别信号A 0，A 1识别的调制技术相对应的相位误差信号。 因此，在脉冲串接收中，由于ODU的信号噪声等于连续接收的信号噪声，可以降低对误码率的影响。

公开(公告)号：US07079597B1

公开(公告)日：2006-07-18

申请号：US10049808

申请日：2000-10-02

申请人： Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H04L27/16 ,  H04L7/00 ,  H04J3/06

CPC分类号： H04L7/042 ,  H04L27/22 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0065 ,  H04L2027/0067

摘要： Frame synchronization is quickly established to acquire an RF channel in a short time. Numerically controlled oscillators 1-1 to 1-3, complex calculation circuits 2-1 to 2-3, band limit filters 3-1 to 3-3, a selector 7, a phase error detection circuit 9, a loop filter 10, and an AFC circuit 11 compose a carrier regeneration loop for removing the frequency error of the carrier included in an in-phase component I and a quadrant component Q of the baseband signal input to the complex calculation circuits 2-1 to 2-3. A timing generator 6 detects which of frame synchronization pattern detection circuits 5-1 to 5-3 has detected a frame synchronization pattern, provides the selector 7 with a selection signal corresponding to the decision result, and sends a switch signal to the AFC circuit 11. Thereafter, the carrier for removing the frequency error included in the baseband signal is regenerated to acquire an RF channel in a short time.

摘要翻译： 快速建立帧同步，以在短时间内获取RF信道。 数字控制振荡器1-1-1-3，复数计算电路2-1-2-3，频带限制滤波器3-1至3-3，选择器7，相位误差检测电路9，环路滤波器10和 AFC电路11构成用于去除包括在同相分量I中的载波的频率误差的载波再生回路和输入到复数计算电路2-1至2-3的基带信号的象限分量Q。 定时发生器6检测哪个帧同步模式检测电路5-1至5-3已经检测到帧同步模式，向选择器7提供与该决定结果相对应的选择信号，并向AFC电路11发送开关信号 。 此后，重新生成用于消除基带信号中包括的频率误差的载波，以在短时间内获取RF信道。

公开(公告)号：US06690745B1

公开(公告)日：2004-02-10

申请号：US09463233

申请日：2000-01-21

申请人： Akihiro Horii ,  Kenichi Shiraishi

发明人： Akihiro Horii ,  Kenichi Shiraishi

IPC分类号： H04L2706

CPC分类号： H04L27/2332 ,  H04L2027/0065

摘要： A received signal phase detecting circuit in provided in which the circuit scale is small. The circuit functions so as to capture a frame synchronizing signal from a demodulated baseband signal, extract a symbol stream during the period of frame synchronizing signal from the demodulated baseband signal through delay circuits (41, 42) at a timing matching the bit stream of the captured synchronizing signal, rotating the phase of a corresponding symbol extracted from the symbol stream when the big in the bit in the bit stream is logic “0” by 80°, outputting the symbol after the phase rotation and a corresponding symbol extracted from the symbol stream when the bit in the bit stream is logic “1” from a 0°/180° phase rotating circuit (43), operating the cumulative average of the output from the 0°/180° phase rotating circuit (43) for a specific period through cumulative averaging circuits (45, 46), rotating the phase of the outputs therefrom through a 22.5° phase rotating circuit (48), and determining the phase of the output therefrom by a phase determining circuit (49).

摘要翻译： 一种接收信号相位检测电路，其中电路规模小。 电路起作用以从解调的基带信号中捕获帧同步信号，在帧同步信号的周期期间，通过延迟电路（41,42），在与 捕获的同步信号，当比特流中的比特中的大比特是逻辑“0”80°时，旋转从符号流提取的对应符号的相位，在相位旋转之后输出符号，并从符号中提取相应的符号 当位流中的位是从0°/ 180°相位旋转电路（43）的逻辑“1”时，对来自0°/ 180°相位旋转电路（43）的输出的累积平均值进行特定操作 通过累积平均电路（45,46），通过22.5°相位旋转电路（48）旋转其输出的相位，并且通过相位确定电路（49）确定其输出的相位。