公开(公告)号：US07251184B2

公开(公告)日：2007-07-31

申请号：US11400404

申请日：2006-04-10

申请人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

发明人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

摘要翻译： 提供一种具有分层位线结构并且即使在低电压下也能执行高速读取操作的半导体存储器件。 子阵列12包括用于对主位线MBL 1充电的第一MOS晶体管PD1和用于对子位线SBL 1 - 1充电的第二MOS晶体管PS 1。 第二MOS晶体管PS 1的源电极连接到电源电压，第一MOS晶体管PD1的源电极通过第四MOS晶体管PD2连接到电源电压。 由于在主位线MBL 1和子位线SBL 1 - 1之间没有电阻，如果使用晶体管来实现导通，则存在该位线之间的电阻，主位线 并且可以高速执行子位线的充电。

公开(公告)号：US20060221754A1

公开(公告)日：2006-10-05

申请号：US11378384

申请日：2006-03-20

申请人： Wataru Abe ,  Mituaki Hayashi ,  Shuji Nakaya

发明人： Wataru Abe ,  Mituaki Hayashi ,  Shuji Nakaya

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C2207/002

摘要： In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray 12 is connected via a first transistor PC1 to a power source voltage, and via a second transistor NC1 to a ground voltage. A main bit line MBLj is connected via a third transistor PD1 to the power source voltage. The gate electrodes of the first transistor PC1 and the second transistor NC1 are connected to the main bit line MBLj, the gate electrode of the third transistor PD1 is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi1 to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.

摘要翻译： 在具有分层位线结构的半导体存储器件中，设置在主位线和子位线之间的转移晶体管阻碍了实现高速和低电压。 子阵列12中的子位线SBL经由第一晶体管PC 1连接到电源电压，并且经由第二晶体管NC 1连接到接地电压。 主位线MBLj经由第三晶体管PD 1连接到电源电压。 第一晶体管PC1和第二晶体管NC1的栅电极连接到主位线MBLj，第三晶体管PD1的栅电极连接到子位线SBL。 在初始状态下，主位线MBLj的电压被控制为H电平，字线WLi 1〜Wlip的电压被控制为L电平。 当执行读取操作时，主位线MBLj的电压转变为L电平，此后，所选字线的电压转换到H电平。

公开(公告)号：US5550775A

公开(公告)日：1996-08-27

申请号：US361551

申请日：1994-12-22

申请人： Wataru Abe ,  Akihiro Yamamoto ,  Takehiko Nakajima ,  Makoto Kojima

发明人： Wataru Abe ,  Akihiro Yamamoto ,  Takehiko Nakajima ,  Makoto Kojima

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H03K17/06 ,  G11C7/00 ,  H03K4/58

CPC分类号： H03K17/063 ,  G11C5/145 ,  G11C8/08

摘要： A semiconductor device comprises: a signal of high voltage not less than the power voltage; a first transistor for transmitting the high voltage signal; a second transistor for electrically charging and discharging the gate potential of the first transistor; and a circuit for generating a pulse signal of which "H" level is a voltage higher than the power voltage by the threshold voltage of the second transistor. The pulse signal generating circuit is connected to the gate electrode of the second transistor. This cancels the drop of a voltage corresponding to the threshold voltage generated at the time when the electric charge is transferred to the gate electrode of the first transistor. Accordingly, even though the power voltage is low, a high voltage signal can be transferred through the first transistor and the word line potential can be boosted to a voltage not less than the power voltage.

摘要翻译： 半导体器件包括：不小于电源电压的高电压信号; 用于发送高电压信号的第一晶体管; 用于对第一晶体管的栅极电位进行充电和放电的第二晶体管; 以及电路，用于产生“H”电平是比第二晶体管的阈值电压高于电源电压的电压的脉冲信号。 脉冲信号发生电路连接到第二晶体管的栅电极。 这取消了与将电荷转移到第一晶体管的栅电极时产生的阈值电压相对应的电压的下降。 因此，即使电源电压低，可以通过第一晶体管传输高电压信号，并且可以将字线电位升高到不低于电源电压的电压。

公开(公告)号：US3986222A

公开(公告)日：1976-10-19

申请号：US618551

申请日：1975-10-01

申请人： Shusuke Miyazaki ,  Yasuo Maehara ,  Wataru Abe ,  Ikuo Shimoda

发明人： Shusuke Miyazaki ,  Yasuo Maehara ,  Wataru Abe ,  Ikuo Shimoda

IPC分类号： E01D2/00 ,  E01D19/00 ,  E01D19/04 ,  E01D101/00 ,  E01D101/40 ,  E04H9/02 ,  F01D25/28 ,  F16F9/10 ,  E01D19/06

CPC分类号： F01D25/28 ,  E01D19/00 ,  E01D19/04 ,  E04H9/022

摘要： There is described a control device particularly suitable for use in the construction of buildings such as continuous girder or truss bridges, elevated highways and the like, for the purpose of controlling vertically imposed loads, more particularly, for the purpose of attenuating mechanical vibrations or impacts as will be caused by braking or starting land vehicles or earthquakes, dispersing horizontally an acting forces at the joint of an upper structure of a bridge such as a girder and a lower structure such as a pier, particularly at a fixed shoe (bridge bearing) on the pier.

摘要翻译： 描述了一种特别适用于施工建筑物的控制装置，例如连续梁或桁架桥，高架路等，用于控制垂直施加的载荷，更具体地说，用于减弱机械振动或冲击的目的 如通过制动或起动陆上车辆或地震而引起的，将作用力水平地分散在诸如桁架的桥梁的上部结构和诸如码头的下部结构的接头处，特别是在固定的鞋（桥接轴承）处， 在码头

公开(公告)号：US07580316B2

公开(公告)日：2009-08-25

申请号：US12119341

申请日：2008-05-12

申请人： Hayashi Mitsuaki ,  Shuji Nakaya ,  Wataru Abe

发明人： Hayashi Mitsuaki ,  Shuji Nakaya ,  Wataru Abe

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C7/18 ,  G11C17/10 ,  G11C2207/002

摘要： Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

摘要翻译： 构成存储单元阵列的子阵列每个都包括位线驱动晶体管，漏极连接到位线，源极连接到具有电源电位的互连，栅极连接到子位线。 多个存储单元分别被设置为使得栅极连接到字线，源极接地，并且是否根据要存储的数据选择漏极连接到子位线。 传输晶体管各自具有连接到位线的栅极，连接到负载晶体管部分的源极和连接到子位线的漏极。

公开(公告)号：US07567480B2

公开(公告)日：2009-07-28

申请号：US12119324

申请日：2008-05-12

申请人： Hayashi Mitsuaki ,  Shuji Nakaya ,  Wataru Abe

发明人： Hayashi Mitsuaki ,  Shuji Nakaya ,  Wataru Abe

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C7/18 ,  G11C17/10 ,  G11C2207/002

摘要： Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

公开(公告)号：US20080175076A1

公开(公告)日：2008-07-24

申请号：US12054263

申请日：2008-03-24

申请人： Mitsuaki HAYASHI ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

发明人： Mitsuaki HAYASHI ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

摘要翻译： 半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路 的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。 作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作 而不受衬底偏置效应的影响。

公开(公告)号：US20060158942A1

公开(公告)日：2006-07-20

申请号：US11151639

申请日：2005-06-14

申请人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

发明人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

摘要翻译： 半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路 的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。 作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作 而不受衬底偏置效应的影响。

公开(公告)号：US20050013038A1

公开(公告)日：2005-01-20

申请号：US10817598

申请日：2004-04-02

申请人： Wataru Abe

发明人： Wataru Abe

IPC分类号： G11B33/08 ,  G11B33/12 ,  G11B17/00

CPC分类号： G11B33/124 ,  G11B33/08

摘要： A magnetic disk device is removable from an apparatus body includes a case, a driving unit, and a connector. The driving unit is installed in the case, and includes a magnetic disk and a rotary driver for rotationally driving the magnetic disk. The connector connects the driving unit and the apparatus body. The case includes an elastic supporting member and a locking member. The elastic supporting member elastically supports the driving unit. The locking member is movable between a locked position and an unlocked position, the driving unit being locked at the locked position and being unlocked at the unlocked position in the case. The locking member moves to the locked position and the unlocked position by operational force from the exterior of the case.

摘要翻译： 磁盘装置可以从设备主体移除，包括壳体，驱动单元和连接器。 驱动单元安装在壳体中，并且包括用于旋转驱动磁盘的磁盘和旋转驱动器。 连接器连接驱动单元和设备主体。 壳体包括弹性支撑构件和锁定构件。 弹性支撑构件弹性地支撑驱动单元。 锁定构件可以在锁定位置和解锁位置之间移动，驱动单元被锁定在锁定位置，并且在壳体中的解锁位置被解锁。 锁定构件通过来自壳体外部的操作力移动到锁定位置和解锁位置。

公开(公告)号：US4557087A

公开(公告)日：1985-12-10

申请号：US528423

申请日：1983-09-01

申请人： Toshiyuki Kitta ,  Wataru Abe

发明人： Toshiyuki Kitta ,  Wataru Abe

IPC分类号： E04C5/10 ,  E04C3/10

CPC分类号： E04C5/10 ,  Y10T428/31529

摘要： A metallic sheath for a posttensioning method wherein an outer peripheral surface or outer and inner peripheral surfaces thereof is (or are) coated with phosphate layer (or layers) and plastic resin layer (or layers) thereupon and preferably further coated with a solid lubricating layer upon the inner peripheral surface of the sheath.The phosphate layer of the outer peripheral surface protect the metallic sheath from corrosion by negative ion within concrete, while, on the other hand, that of the inner peripheral surface prevents the electrochemical corrosion between the inner peripheral surface of the sheath and tendon.Moreover, if a solid lubricating, layer is provided at the inner peripheral surface of the sheath, the sliding friction between the metallic sheath and tendon can be decreased so that prestressed force can be increased as much.

摘要翻译： 一种用于后拉伸方法的金属护套，其外表面或外周表面或外周表面或其外周表面（或被）涂覆有磷酸盐层（或层）和塑料树脂层（或层），并且优选地进一步涂覆有固体润滑层 在护套的内周表面上。 外周表面的磷酸盐层通过负离子保护金属护套免受混凝土的腐蚀，另一方面，内周面的内部表面防止了护套内周面与腱之间的电化学腐蚀。 此外，如果在护套的内周面设置固体润滑层，则可以减少金属护套和腱之间的滑动摩擦，从而可以增加预应力。