公开(公告)号：US20060239109A1

公开(公告)日：2006-10-26

申请号：US11400404

申请日：2006-04-10

申请人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

发明人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

摘要翻译： 提供一种具有分层位线结构并且即使在低电压下也能执行高速读取操作的半导体存储器件。 子阵列12包括用于对主位线MBL 1充电的第一MOS晶体管PD1和用于对子位线SBL 1 - 1充电的第二MOS晶体管PS 1。 第二MOS晶体管PS 1的源电极连接到电源电压，第一MOS晶体管PD1的源电极通过第四MOS晶体管PD2连接到电源电压。 由于在主位线MBL 1和子位线SBL 1 - 1之间没有电阻，如果使用晶体管来实现导通，则存在该位线之间的电阻，主位线 并且可以高速执行子位线的充电。

公开(公告)号：US07251184B2

公开(公告)日：2007-07-31

申请号：US11400404

申请日：2006-04-10

申请人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

发明人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

摘要翻译： 提供一种具有分层位线结构并且即使在低电压下也能执行高速读取操作的半导体存储器件。 子阵列12包括用于对主位线MBL 1充电的第一MOS晶体管PD1和用于对子位线SBL 1 - 1充电的第二MOS晶体管PS 1。 第二MOS晶体管PS 1的源电极连接到电源电压，第一MOS晶体管PD1的源电极通过第四MOS晶体管PD2连接到电源电压。 由于在主位线MBL 1和子位线SBL 1 - 1之间没有电阻，如果使用晶体管来实现导通，则存在该位线之间的电阻，主位线 并且可以高速执行子位线的充电。

公开(公告)号：US20090021973A1

公开(公告)日：2009-01-22

申请号：US12119341

申请日：2008-05-12

申请人： Mitsuaki Hayashi ,  Shuji Nakaya ,  Wataru Abe

发明人： Mitsuaki Hayashi ,  Shuji Nakaya ,  Wataru Abe

IPC分类号： G11C5/06 ,  G11C8/08 ,  G11C5/14

CPC分类号： G11C8/12 ,  G11C7/18 ,  G11C17/10 ,  G11C2207/002

摘要： Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

摘要翻译： 构成存储单元阵列的子阵列每个都包括位线驱动晶体管，漏极连接到位线，源极连接到具有电源电位的互连，栅极连接到子位线。 多个存储单元分别被设置为使得栅极连接到字线，源极接地，并且是否根据要存储的数据选择漏极连接到子位线。 传输晶体管各自具有连接到位线的栅极，连接到负载晶体管部分的源极和连接到子位线的漏极。

公开(公告)号：US20060158942A1

公开(公告)日：2006-07-20

申请号：US11151639

申请日：2005-06-14

申请人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

发明人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

摘要翻译： 半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路 的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。 作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作 而不受衬底偏置效应的影响。

公开(公告)号：US07420868B2

公开(公告)日：2008-09-02

申请号：US11405488

申请日：2006-04-18

申请人： Mitsuaki Hayashi ,  Shuji Nakaya ,  Wataru Abe

发明人： Mitsuaki Hayashi ,  Shuji Nakaya ,  Wataru Abe

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C7/18 ,  G11C17/10 ,  G11C2207/002

摘要： Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

摘要翻译： 构成存储单元阵列的子阵列每个都包括位线驱动晶体管，漏极连接到位线，源极连接到具有电源电位的互连，栅极连接到子位线。 多个存储单元分别被设置为使得栅极连接到字线，源极接地，并且是否根据要存储的数据选择漏极连接到子位线。 传输晶体管各自具有连接到位线的栅极，连接到负载晶体管部分的源极和连接到子位线的漏极。

公开(公告)号：US07382657B2

公开(公告)日：2008-06-03

申请号：US11151639

申请日：2005-06-14

申请人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

发明人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

IPC分类号： G11C16/06

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

摘要翻译： 半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路 的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。 作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作 而不受衬底偏置效应的影响。

公开(公告)号：US20060002212A1

公开(公告)日：2006-01-05

申请号：US11025138

申请日：2004-12-30

申请人： Shuji Nakaya ,  Mitsuaki Hayashi ,  Masakazu Kurata

发明人： Shuji Nakaya ,  Mitsuaki Hayashi ,  Masakazu Kurata

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C17/14 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/1202 ,  G11C2029/1204

摘要： An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.”

摘要翻译： 连接到输出缓冲电路的锁存电路的输出端和反相输出端彼此切换，由此“0”或“1”的数据与存储单元的漏极之间的关系为 连接或未连接到位线被更改。 此外，读出放大器的输入通过测试控制信号固定在接地电位，从而在输出缓冲电路的输出为“L”的情况下确认正逻辑，而负逻辑为 在输出缓冲电路的输出为“H”的情况下确认。

公开(公告)号：US07489571B2

公开(公告)日：2009-02-10

申请号：US11674184

申请日：2007-02-13

申请人： Shuji Nakaya ,  Mitsuaki Hayashi

发明人： Shuji Nakaya ,  Mitsuaki Hayashi

IPC分类号： G06F12/16 ,  G11C8/12 ,  G11C29/00

CPC分类号： G11C29/846 ,  G11C29/785

摘要： A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal. The switching circuit inputs the controlling signal and data outputted from a read only storage device which is selected by an address signal and outputs the data from the read only storage device. The switching circuit inverts a defective bit of the data outputted from the read only storage device in response to receipt of the controlling signal from the bit storage circuit and outputs data whose defective bit is inverted instead of the data outputted from the read only storage device.

摘要翻译： 提供半导体器件用于输出从只读存储器读取的数据。 半导体器件包括只读存储器件，包括存储器单元，用于向每个只读存储器件发送地址信号的地址信号线，以及输入地址信号的开关器件。 地址信号表示存储要读取的数据的存储单元的地址。 开关装置包括地址存储电路，位存储电路和开关存储电路。 地址存储电路存储只读存储装置的缺陷存储单元的地址信息，并且检测存储由地址信号选择的数据的存储单元是否包含有缺陷的存储单元。 位存储电路存储指示存储在包括有缺陷存储单元的存储单元中的数据的哪一位的位信息，并输出控制信号。 切换电路输入从地址信号选择的只读存储装置输出的控制信号和数据，并从只读存储装置输出数据。 开关电路响应于来自位存储电路的控制信号的接收而反转从只读存储装置输出的数据的有缺陷的位，并且输出其缺陷位被反相的数据，而不是从只读存储装置输出的数据。

公开(公告)号：US07110307B2

公开(公告)日：2006-09-19

申请号：US11025138

申请日：2004-12-30

申请人： Shuji Nakaya ,  Mitsuaki Hayashi ,  Masakazu Kurata

发明人： Shuji Nakaya ,  Mitsuaki Hayashi ,  Masakazu Kurata

IPC分类号： G11C11/34

CPC分类号： G11C17/12 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C17/14 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/1202 ,  G11C2029/1204

摘要： An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.”

摘要翻译： 与输出缓冲电路连接的锁存电路的输出端和反相输出端彼此切换，由此“0”或“1”的数据与存储单元的漏极之间的关系为 连接或未连接到位线被更改。 此外，读出放大器的输入通过测试控制信号固定在接地电位，从而在输出缓冲电路的输出为“L”的情况下确认正逻辑，而负逻辑为 在输出缓冲电路的输出为“H”的情况下确认。

公开(公告)号：US06800524B2

公开(公告)日：2004-10-05

申请号：US10420919

申请日：2003-04-23

申请人： Mitsuaki Hayashi ,  Shuji Nakaya

发明人： Mitsuaki Hayashi ,  Shuji Nakaya

IPC分类号： H01L21336

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/11226

摘要： The object of the present invention is directed to shorten a manufacturing TAT when changing a stored data of a mask ROM incorporated into a semiconductor integrated circuit device with multi-layered structure, and to improve a manufacturing yield. For example, when the semiconductor integrated circuit device comprising an interconnection layer with five layers are manufactured, when fabricating samples or prototypes where data to be written to the mask ROM is frequently changed, the manufacturing TAT is shortened by means of configuring a bit line as a fifth layer of metal interconnection layer of an uppermost layer, and an interlayer dielectric (ILD) layer just below it as a forming layer of a via hole for use in data writing. During the manufacture of mass-produced products after determining the ROM data, it is possible to decrease the number of layers for configuring the memory cell by means of forming the bit line by the first metal interconnection layer of a lowermost layer, and configuring the ILD layer just below it as a forming layer of the via hole for use in data writing, to improve the manufacturing yield by reducing manufacturing process steps of the memory cell.

摘要翻译： 本发明的目的是缩短在结合到具有多层结构的半导体集成电路器件中的掩模ROM的存储数据的存储数据时的制造TAT，并提高制造成品率。 例如，当制造包括具有五层的互连层的半导体集成电路器件时，当制造要写入掩模ROM的数据经常改变的样品或原型时，通过将位线配置为 最上层的第五层金属互连层，以及其正下方的层间绝缘膜（ILD）层作为用于数据写入的通孔的形成层。 在确定ROM数据之后制造批量生产的产品时，可以通过由最下层的第一金属互连层形成位线来减少用于配置存储单元的层数，并且配置ILD 作为用于数据写入的通孔的形成层，通过减小存储单元的制造工艺步骤来提高制造成品率。