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公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译： 公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。 杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。 已知的光栅结构被构建在衬底上。 实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。
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公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。
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公开(公告)号：US07052575B1
公开(公告)日：2006-05-30
申请号：US09845454
申请日：2001-04-30
IPC分类号： C23F1/00
CPC分类号： H01L21/67253 , H01J37/32935 , H01L21/67063 , H01L22/34
摘要： A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.
摘要翻译： 提供了一种用于调节蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可接受性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。
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14.发明授权公开(公告)号：US06931618B1
公开(公告)日：2005-08-16
申请号：US10050472
申请日：2002-01-16
摘要： A system for selectively generating and feeding forward reticle fabrication data is provided. The system includes components for fabricating a reticle and a control system operatively connected to the fabricating components, where the control system can control the operation of the fabricating components. The control system bases its control of the fabricating components, at least in part, on feed forward control information generated by a processor that analyzes scatterometry based reticle fabrication data gathered from measurement components. The scatterometry data is compared to data stored in a signature data store that facilitates analyzing gathered scatterometry signatures to produce feed forward control information that can be employed to manipulate subsequent reticle fabrication processes and/or apparatus.
摘要翻译： 提供了一种用于选择性地生成和馈送标线制造数据的系统。 该系统包括用于制造掩模版的部件和可操作地连接到制造部件的控制系统，其中控制系统可以控制制造部件的操作。 控制系统至少部分地基于由分析从测量部件收集的基于散射仪的掩模版制造数据的处理器生成的前馈控制信息的制造部件的控制。 将散射测量数据与存储在签名数据存储器中的数据进行比较，其有助于分析所收集的散射光标签以产生可用于操纵随后的标线制造工艺和/或设备的前馈控制信息。
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公开(公告)号：US06912438B2
公开(公告)日：2005-06-28
申请号：US10277016
申请日：2002-10-21
CPC分类号： H01L22/20 , G01N21/4738 , H01L2924/0002 , H01L2924/00
摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.
摘要翻译： 公开了用于监测和控制半导体制造工艺的系统和方法。 根据基于散射法的技术进行测量，该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。 可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。 另外，例如，可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。 在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产，因为测试光栅结构可能不需要在晶片内形成，并且还有助于对实际影响芯片性能的元件的控制。
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公开(公告)号：US06878560B1
公开(公告)日：2005-04-12
申请号：US10302091
申请日：2002-11-22
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G05B2219/31457 , G05B2219/32191 , G05B2219/45031 , H01L2924/0002 , H01L2924/00
摘要： A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
摘要翻译： 由多个工厂组成的系统，其可操作地耦合并且共享来自公共框架的数据以用于生产。 该晶圆厂可以通过互联网，蜂窝，光学，固定电话，微波和卫星通信装置等耦合。 可以将数据传送到中央集成的相关实体或从多个分散的相关实体传送到和/或从中央集成的相关实体接收数据。 制造厂发送和接收与生产信息相关的相关数据，例如公差，关键尺寸，几何形状等。 相关实体具有通过对接收到的相关数据执行概率计算并利用所得到的信息来维持远程位置处的相关参数来增加产量的能力。 执行的计算可以包括诸如贝叶斯推理等的计算。 该系统固有地排除了在不同晶圆厂或模具位置之间物理传输参数测试实体的必要性。
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公开(公告)号：US06741445B1
公开(公告)日：2004-05-25
申请号：US10050458
申请日：2002-01-16
IPC分类号： H01T2300
CPC分类号： H01L21/67253
摘要： A system and methodology is provided for monitoring and controlling static charge during wafer and mask fabrication. The static charge on a target device is monitored. If the static charge becomes too high, corrective actions are taken to reduce the static charge. An antistatic solution is dispensed on the target device. The system and methodology provided reduce damage resulting from electrostatic discharge during fabrication. The system and methodology also reduce delays during fabrication by automatically controlling static charge without the need for manual intervention.
摘要翻译： 提供了一种用于在晶片和掩模制造期间监测和控制静电荷的系统和方法。 监视目标设备上的静电荷。 如果静电荷过高，则采取纠正措施减少静电。 抗静电溶液分配在目标装置上。 所提供的系统和方法减少了制造过程中静电放电造成的损坏。 该系统和方法还通过自动控制静电而减少制造过程中的延迟，而无需人工干预。
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18.发明授权Use of scatterometry/reflectometry to measure thin film delamination during CMP 有权在CMP期间使用散射/反射测量薄膜分层公开(公告)号：US06702648B1
公开(公告)日：2004-03-09
申请号：US10277559
申请日：2002-10-22
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/12
摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.
摘要翻译： 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。
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19.发明授权Sensor to predict void free films using various grating structures and characterize fill performance 失效传感器预测使用各种光栅结构的无空隙膜，并表征填充性能公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。
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公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译： 提供了一种用于调节开发过程的时间和温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的显影进展。 该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。 该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置，以调节晶片各部分的温度。
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