公开(公告)号：US20220028460A1

公开(公告)日：2022-01-27

申请号：US17202627

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

公开(公告)号：US20230395178A1

公开(公告)日：2023-12-07

申请号：US18453567

申请日：2023-08-22

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/20 ,  G11C29/12005 ,  G11C2029/1802

Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.

公开(公告)号：US20230087010A1

公开(公告)日：2023-03-23

申请号：US17695086

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.

公开(公告)号：US20220351780A1

公开(公告)日：2022-11-03

申请号：US17869081

申请日：2022-07-20

Applicant: KIOXIA CORPORATION

Inventor： Hideki YAMADA ,  Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US20210089392A1

公开(公告)日：2021-03-25

申请号：US16807220

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA ,  Ryo YAMAKI ,  Osamu TORII ,  Naomi TAKEDA

IPC: G06F11/10 ,  G06F9/30

Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.