公开(公告)号：US20220180942A1

公开(公告)日：2022-06-09

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Takayuki MIYAZAKI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US20210399049A1

公开(公告)日：2021-12-23

申请号：US17348839

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takahiko IIZUKA ,  Daisaburo TAKASHIMA ,  Ryu OGIWARA ,  Rieko FUNATSUKI ,  Yoshiki KAMATA ,  Misako MOROTA ,  Yoshiaki ASAO ,  Yukihiro NOMURA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.