公开(公告)号：US20220084587A1

公开(公告)日：2022-03-17

申请号：US17349095

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takayuki MIYAZAKI

IPC: G11C13/00 ,  H01L27/24

Abstract: A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.

公开(公告)号：US20210295892A1

公开(公告)日：2021-09-23

申请号：US17002512

申请日：2020-08-25

Applicant: KIOXIA CORPORATION

Inventor： Takayuki MIYAZAKI

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/06 ,  G11C5/02

Abstract: A semiconductor storage device includes a first wiring, a second wiring, a memory cell including a first element configured to store data and a second element connected to the first element, the memory cell having a first end connected to the first wiring and a second end connected to the second wiring, and a control circuit configured to apply a voltage that increase with a first slope and then with a second slope that is smaller than the first slope, to the memory cell using the first wiring and the second wiring.

公开(公告)号：US20210090650A1

公开(公告)日：2021-03-25

申请号：US16943638

申请日：2020-07-30

Applicant: KIOXIA CORPORATION

Inventor： Yusuke NIKI ,  Atsushi KAWASUMI ,  Takayuki MIYAZAKI

IPC: G11C13/00 ,  H01L45/00

Abstract: According to one embodiment, a device includes first lines transmitting a first signals; second lines receiving the first signals; and a first circuit including a first selector coupled to the first lines, a second selector coupled to the second lines, third lines and a fourth lines between the first and second selectors. Each of the third lines stores the second signals, each of the fourth lines stores the third signals. The first circuit counts a first number of second signals equivalent to the corresponding first signal; counts a second number of third signals equivalent to corresponding first signal of the first signals; and couples either the third or the fourth lines to the first and second lines via the first and second selectors, based on a result of comparison between the first and the second numbers.

公开(公告)号：US20240282359A1

公开(公告)日：2024-08-22

申请号：US18582433

申请日：2024-02-20

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Takayuki MIYAZAKI ,  Takashi INUKAI

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.

公开(公告)号：US20240057314A1

公开(公告)日：2024-02-15

申请号：US18448703

申请日：2023-08-11

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Takayuki MIYAZAKI ,  Masaharu WADA ,  Takashi INUKAI

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/33 ,  H01L29/7869 ,  H01L29/78642 ,  H10B12/48

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a capacitor that includes a first electrode extending in a first direction intersecting the semiconductor substrate and a second electrode facing the first electrode. A first conductive layer is above the capacitor and extends in a second direction. A semiconductor layer penetrates the first conductive layer in the first direction. A first conductor can be above or below the first conductive layer and electrically connected to the first conductive layer. A first insulating film is between the first conductive layer and the semiconductor layer. A second conductive layer extends in the second direction and is electrically connected to the first conductive layer via the first conductor.

公开(公告)号：US20230410886A1

公开(公告)日：2023-12-21

申请号：US18081265

申请日：2022-12-14

Applicant: Kioxia Corporation

Inventor： Takeshi SUGIMOTO ,  Takayuki MIYAZAKI

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C11/4099 ,  G11C11/4096

Abstract: A memory includes first cell layers respectively including first cells, and a second cell layer including dummy cells. A first wire is connected to the first cells arrayed in a first direction. A second wire is connected to the dummy cells arrayed in the first direction. A third wire is connected to the first cells and one of the dummy cells arrayed in a second direction. A fourth wire is connected to the third wires arrayed in a third direction. A first voltage is applied to a selected first wire when reading data from a selected first cell, and transmits a read data to a selected fourth wire connected to the selected first cell. A reference voltage is applied to a non-selected fourth wire. A second voltage is applied to a selected second wire provided with the dummy cell between the selected second wire and the non-selected fourth wire.

公开(公告)号：US20210089240A1

公开(公告)日：2021-03-25

申请号：US16803883

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Reika TANAKA ,  Takayuki MIYAZAKI ,  Masumi SAITOH

IPC: G06F3/06

Abstract: A storage device includes a substrate, first wirings arranged in a first direction and extending in a second direction, second wirings arranged in the second direction and extending in the first direction, resistance portions between the first and second wirings, third wirings between the second wirings and the substrate, arranged in the second direction and extending in a third direction, semiconductor portions each connected to second and third wirings, a fourth wiring extending in the second direction and facing the semiconductor portions, insulating portions between the semiconductor portions and the fourth wiring, and a contact connected to each first wiring. The semiconductor portions include a first portion and a second portion closer to the contact, and a length in the second direction of an insulating portion between the first portion and the fourth wiring is greater than that of another insulating portion between the second portion and the fourth wiring.

公开(公告)号：US20220180942A1

公开(公告)日：2022-06-09

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Takayuki MIYAZAKI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US20210280243A1

公开(公告)日：2021-09-09

申请号：US17122063

申请日：2020-12-15

Applicant: Kioxia Corporation

Inventor： Takayuki MIYAZAKI

IPC: G11C13/00

Abstract: A memory includes first-lines, second-lines, and memory cells. Third-lines are provided to respectively correspond to groups each comprising m (m≥2) lines of the first-lines. A first selector selects a certain one of the first-lines from the groups and to connect the selected first-lines to the third-lines corresponding to the groups. Fourth-lines correspond to the third-lines. A second selector selects one of the third-lines and to connect the fourth-line to the selected third-line. A third selector selects a certain one of the second-lines. A first driver applied a voltage to the fourth-line. A second driver is connected to the third selector. The first driver charges the third-line corresponding to the first-line selected from the groups via the fourth-line. The first and second selectors bring the selected first-line and the third-line corresponding the first-line to an electrically floating state. The second driver applies a voltage to the selected second-line.

公开(公告)号：US20240324169A1

公开(公告)日：2024-09-26

申请号：US18601832

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi INUKAI ,  Tsuneo INABA ,  Takayuki MIYAZAKI

IPC: H10B12/00 ,  H01L23/482 ,  H01L23/538

CPC classification number: H10B12/0335 ,  H01L23/4824 ,  H01L23/538 ,  H10B12/485 ,  H10B12/488

Abstract: According to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.