公开(公告)号：US20240304245A1

公开(公告)日：2024-09-12

申请号：US18593570

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A semiconductor memory device includes bit lines, memory cells that are respectively connected to the bit lines, sense amplifier units that are respectively connected to the bit lines, and each of which includes m latch circuits, and a logic control circuit configured to input data to the m latch circuits and control a write operation on each of the memory cells using the data input to the m latch circuits. The logic control circuit executes an operation to write n bits to each of the memory cells, where n is 2 or more and greater than m, by executing a plurality of write operations, including a first write operation executed on the memory cells by inputting first m bits of data to the m latch circuits, and a second write operation executed on the memory cells by inputting second m bits of data to the m latch circuits.

公开(公告)号：US20220301636A1

公开(公告)日：2022-09-22

申请号：US17447464

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Kyosuke SANO ,  Kazutaka IKEGAMI ,  Takashi MAEDA ,  Rieko FUNATSUKI

IPC: G11C16/26 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/30

Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

公开(公告)号：US20220284962A1

公开(公告)日：2022-09-08

申请号：US17445614

申请日：2021-08-23

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Takashi MAEDA

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: A memory system according to an embodiment includes first to sixth word lines, a plurality of memory pillars and a control circuit. The control circuit performs an initial write operation in which a threshold voltage of a subject memory cell is increased from a first level to a second level, a first write operation after the initial write operation and a second write operation after the first write operation. The control circuit is configured to perform the initial write operation on the third memory cell and the fourth memory cells, the first write operation on the third memory cells, the first write operation on the fourth memory cells, the second write operation on the fifth memory cells, the second write operation on the sixth memory cells, and the initial write operation on the first memory cells and the second memory cells.

公开(公告)号：US20230197177A1

公开(公告)日：2023-06-22

申请号：US17816836

申请日：2022-08-02

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Takashi MAEDA ,  Reiko SUMI

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3481 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

公开(公告)号：US20230410913A1

公开(公告)日：2023-12-21

申请号：US18068605

申请日：2022-12-20

Applicant: KIOXIA CORPORATION

Inventor： Reiko SUMI ,  Kazutaka IKEGAMI

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459

Abstract: A semiconductor memory device comprises: a semiconductor layer extending in a first direction; a first and second conductive layer facing the semiconductor layer from one side and the other side in a second direction; and a charge storage layer comprising portions provided between the semiconductor layer and first conductive layer and between the semiconductor layer and second conductive layer. The semiconductor memory device is configured to execute erase operation, first write operation, and second write operation. In the first write operation, the first and second conductive layers are applied with first program voltage. In the second write operation, the first conductive layer is applied with second program voltage, and second conductive layer is applied with second voltage lower than the second program voltage. The second write operation is executed after execution of the erase operation and before execution of the first write operation.

公开(公告)号：US20230297245A1

公开(公告)日：2023-09-21

申请号：US17899974

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Sumiko DOMAE ,  Kazutaka IKEGAMI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659 ,  G06F3/0653

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

公开(公告)号：US20220180942A1

公开(公告)日：2022-06-09

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Takayuki MIYAZAKI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US20240244839A1

公开(公告)日：2024-07-18

申请号：US18435113

申请日：2024-02-07

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Shingo NAKAZAWA

IPC: H10B41/35 ,  H10B41/27 ,  H10B41/47

CPC classification number: H10B41/35 ,  H10B41/27 ,  H10B41/47

Abstract: A memory system for low power consumption and high speed read operation in the memory system includes a source line, a string select line having i layers, a first word line having i layers, a second word line having i layers, a select gate line having 1 layer which is divided into 2n, a plurality of memory pillars and a control circuit. Each of the plurality of memory pillars includes a first string and a second string. The first string includes a first transistor, i first memory cells and j second memory cells. The first transistor, the i first memory cells, and the j second memory cells are electrically connected in series. The second string includes a second transistor, i third memory cells, and j fourth memory cells. The second transistor, the i third memory cells, and the j fourth memory cells are electrically connected in series.

公开(公告)号：US20240071477A1

公开(公告)日：2024-02-29

申请号：US18500478

申请日：2023-11-02

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Rieko FUNATSUKI ,  Nobuyuki MOMO ,  Hidehiro SHIGA

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory system for speeding up a read operation in the memory system includes a first pillar, a first string including a first transistor and a first memory cell, a second string including a second transistor and a second memory cell, a first bit line, a first gate line, a first word line, a second gate line, a second word line and a control circuit. When the control circuit executes a read operation with respect to the first memory cell, the control circuit is configured to apply a read voltage to the first word line, apply a voltage turning off the second memory cell regardless of an electric charge stored in the second memory cell to the second word line, apply a voltage turning on the first transistor to the first gate line, and apply a voltage turning on the second transistor to the second gate line.

公开(公告)号：US20240046995A1

公开(公告)日：2024-02-08

申请号：US18176507

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Kyosuke SANO ,  Kazutaka IKEGAMI ,  Takashi MAEDA

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/3459 ,  G11C16/08 ,  G11C16/26 ,  G11C16/0483

Abstract: A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.