公开(公告)号：US20230297289A1

公开(公告)日：2023-09-21

申请号：US18322104

申请日：2023-05-23

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0652

Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

公开(公告)号：US20230297247A1

公开(公告)日：2023-09-21

申请号：US17941388

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Yuki SASAKI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

Abstract: According to one embodiment, a controller of a memory system writes, in response to receiving from the host a write command specifying a logical address, data received from the host to a first write destination block. The controller manages a first list and first storage location information, the first list including a plurality of logical addresses corresponding respectively to write-uncompleted data, and the first storage location information indicating a storage location at a beginning of a write-uncompleted region in the first write destination block. In a case where a power loss has occurred without notice from the host, the controller writes the first list and the first storage location information to the nonvolatile memory using power from a capacitor.

公开(公告)号：US20230014508A1

公开(公告)日：2023-01-19

申请号：US17653324

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G11C8/08

Abstract: According to one embodiment, a controller manages a first set of blocks and a second set of blocks. The controller allocates a second block included in the second set of blocks to a first block included in the first set of blocks. In response to receiving one or more write command specifying the first block, the controller writes data associated with the one or more received write commands to the second block in units of a second minimum write size. When the first block is filled with data that has been written to the first block and unwritten region remains in the second block, the controller deallocates the second block from the first block, and allocates the deallocated second block to a write destination block other than the first block.

公开(公告)号：US20220300182A1

公开(公告)日：2022-09-22

申请号：US17468163

申请日：2021-09-07

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.

公开(公告)号：US20220156182A1

公开(公告)日：2022-05-19

申请号：US17590310

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro FUKUTOMI ,  Kenichiro YOSHII ,  Shinichi KANNO ,  Shigehiro ASANO

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US20220113910A1

公开(公告)日：2022-04-14

申请号：US17557148

申请日：2021-12-21

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.

公开(公告)号：US20210064520A1

公开(公告)日：2021-03-04

申请号：US16815894

申请日：2020-03-11

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F12/02 ,  G06F12/1009 ,  G06F13/16 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.

公开(公告)号：US20210064289A1

公开(公告)日：2021-03-04

申请号：US16815926

申请日：2020-03-11

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.

公开(公告)号：US20250021477A1

公开(公告)日：2025-01-16

申请号：US18768292

申请日：2024-07-10

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F12/02

Abstract: According to one embodiment, a memory system includes a controller. The controller manages a plurality of flags corresponding to a plurality of physical addresses. In response to receiving a read command from a host, the controller acquires from a first management table a physical address mapped to a logical address specified by the read command, and reads data from a nonvolatile memory based on the acquired physical address. The controller determines whether or not to transmit the read data to the host based on whether a current status of the flag corresponding to the acquired physical address is set to a first value indicating valid data or to a second value indicating invalid data.

公开(公告)号：US20240372567A1

公开(公告)日：2024-11-07

申请号：US18771866

申请日：2024-07-12

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO ,  Hironori UCHIKAWA

IPC: H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/40 ,  G11C29/52 ,  H03M13/00 ,  H03M13/03 ,  H03M13/35

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.