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    SYNDROME CALCULATION FOR ERROR DETECTION AND ERROR CORRECTION
    1.
    发明公开
    SYNDROME CALCULATION FOR ERROR DETECTION AND ERROR CORRECTION 审中-公开

    公开(公告)号：US20230318628A1

    公开(公告)日：2023-10-05

    申请号：US18330669

    申请日：2023-06-07

    Applicant: Kioxia Corporation

    Inventor： Hironori UCHIKAWA

    IPC: H03M13/15

    CPC classification number: H03M13/159 ,  H03M13/1177

    Abstract: A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权

    公开(公告)号：US20230139971A1

    公开(公告)日：2023-05-04

    申请号：US18148060

    申请日：2022-12-29

    Applicant: Kioxia Corporation

    Inventor： Shinichi KANNO ,  Hironori UCHIKAWA

    IPC: H03M13/29 ,  G06F11/10 ,  H03M13/35 ,  G11C29/52 ,  G06F13/16 ,  G06F13/40 ,  H03M13/00

    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

    MEMORY SYSTEM AND METHOD FOR CONTROLLING NON-VOLATILE MEMORY
    3.
    发明申请
    MEMORY SYSTEM AND METHOD FOR CONTROLLING NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220278695A1

    公开(公告)日：2022-09-01

    申请号：US17463818

    申请日：2021-09-01

    Applicant: Kioxia Corporation

    Inventor： Yuta KUMANO ,  Hironori UCHIKAWA

    IPC: H03M13/15 ,  G06F11/10

    Abstract: A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller executes a first decoding process of reading data encoded by an error correction code from the non-volatile memory and repeatedly executing bounded distance decoding on a symbol group protected by each of component codes included in N component code groups; executes a second decoding process of repeatedly executing decoding exceeding a bounded distance in units of component codes for an error symbol group determined to include an error due to a syndrome of a component code included in the N component code groups when the first decoding process fails; executes a rollback process when the first decoding process executed after the second decoding process fails; and changes a parameter used in the second decoding process and further executes the second decoding process when it is detected that the second decoding process is not progressed.

    MEMORY SYSTEM
    4.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210273655A1

    公开(公告)日：2021-09-02

    申请号：US17005282

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Yuta KUMANO ,  Hironori UCHIKAWA

    IPC: H03M13/15 ,  H03M13/11 ,  G06F11/07

    Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores a multidimensional error correction code in which each of a plurality of symbol groups is encoded by both a first component code and a second component code. The memory controller reads the error correction code from the nonvolatile memory, executes a first decoding process using the first component code and the second component code, and when the first decoding process fails, executes a second decoding process on an error symbol group. The second decoding process includes a process of selecting the positions of a plurality of symbols whose values included in the error symbol group are to be inverted according to a decision rule. The decision rule includes a rule for cyclically shifting a position selected for the second decoding process at to decide the position for the second decoding process at the next time.

    MEMORY SYSTEM
    5.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210081275A1

    公开(公告)日：2021-03-18

    申请号：US16804940

    申请日：2020-02-28

    Applicant: KIOXIA CORPORATION

    Inventor： Yuta KUMANO ,  Hironori UCHIKAWA

    IPC: G06F11/10 ,  H03M13/15

    Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.

    MEMORY SYSTEM AND CONTROL METHOD
    6.
    发明申请
    MEMORY SYSTEM AND CONTROL METHOD 有权

    公开(公告)号：US20250096816A1

    公开(公告)日：2025-03-20

    申请号：US18821531

    申请日：2024-08-30

    Applicant: Kioxia Corporation

    Inventor： Yuta KUMANO ,  Hironori UCHIKAWA

    IPC: H03M13/11 ,  H03M13/00

    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. Further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.

    MULTIDIMENSIONAL ENCODING AND DECODING IN MEMORY SYSTEM
    8.
    发明申请
    MULTIDIMENSIONAL ENCODING AND DECODING IN MEMORY SYSTEM 有权

    公开(公告)号：US20230083269A1

    公开(公告)日：2023-03-16

    申请号：US17680164

    申请日：2022-02-24

    Applicant: KIOXIA CORPORATION

    Inventor： Yuta KUMANO ,  Hironori UCHIKAWA

    IPC: H03M13/11 ,  H03M13/15 ,  H03M13/45 ,  H03M13/37 ,  G06F11/10

    Abstract: A memory system includes an encoder and a decoder. The encoder is configured to generate multi-dimensionally-coded data to be written into the non-volatile memory. Data bits of the multi-dimensionally-coded data are grouped into first and second dimensional codes with respect to first and second dimensions, respectively. The decoder is configured to, with respect to each of the first and second dimensional codes included in read multi-dimensionally-coded data, generate a syndrome value of the dimensional code, generate low-reliability location information, generate a soft-input value based on the syndrome value and the low-reliability location information, decode the dimensional code through correction of the dimensional code using the soft-input value, and store modification information indicating a bit of the dimensional code corrected through the correction and reliability information indicating reliability of the correction. The decoder generates the soft-input value also based on the modification information and the reliability information in the memory.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210398598A1

    公开(公告)日：2021-12-23

    申请号：US17348814

    申请日：2021-06-16

    Applicant: Kioxia Corporation

    Inventor： Taira SHIBUYA ,  Noboru SHIBATA ,  Hironori UCHIKAWA

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/12 ,  G11C16/08 ,  G11C7/06

    Abstract: A semiconductor memory device according to an embodiment includes first memory cells, second memory cells, and a controller. A threshold voltage of each of the first memory cells and the second memory cells is included in one of first through sixteenth state. 8-bit data that includes a first through eighth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell. The controller is configured to: apply in parallel a plurality of types of read voltages to each of the first memory cells and the second memory cells and externally output data confirmed based on first data read from the first memory cells and second data read from the second memory cells.

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