公开(公告)号：US20110204908A1

公开(公告)日：2011-08-25

申请号：US13006325

申请日：2011-01-13

申请人： Kenichi Tada ,  Koki Tsutsumida ,  Masatoshi Kawashima ,  Hideki Hayashi ,  Tsutomu Sato ,  Koichi Sugimoto

发明人： Kenichi Tada ,  Koki Tsutsumida ,  Masatoshi Kawashima ,  Hideki Hayashi ,  Tsutomu Sato ,  Koichi Sugimoto

IPC分类号： G01R31/3187

CPC分类号： G01R31/318594 ,  G01R31/318552

摘要： A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit.

摘要翻译： 半导体器件被设计为便于分析采用多相时钟的集成电路的故障的位置和原因。 为此，半导体器件设置有检测在集成电路中发生操作问题的错误检测单元，时钟状态保持单元，其保持预定项中的相位信息为两维或多次， 相位时钟和输出单元，当错误检测单元检测到集成电路中发生操作的问题时，输出两相或更多相位时钟的预定项中的相位的信息。

公开(公告)号：US07299392B2

公开(公告)日：2007-11-20

申请号：US10291599

申请日：2002-11-12

申请人： Hisakazu Date ,  Toyohito Ikeya ,  Masatoshi Kawashima

发明人： Hisakazu Date ,  Toyohito Ikeya ,  Masatoshi Kawashima

IPC分类号： G01R31/28

CPC分类号： G01R31/31922

摘要： A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.

摘要翻译： 公开了具有能够进行高性能测试操作的测试时钟发生电路和能够设定高精度定时裕度的半导体集成电路器件的设计方法的半导体集成电路器件。 具有寄存器顺序电路和时钟输出控制电路的测试时钟发生电路设置在脉冲发生电路和逻辑电路之间。 当测试操作激活时，停止在脉冲发生电路中产生的时钟脉冲到逻辑电路的传送，并且使用在脉冲发生电路中产生的脉冲信号来输出操作逻辑电路的测试时钟脉冲，通过控制时钟转移 控制电路具有根据寄存器的设置信息的顺序电路。 测试时钟发生电路包括利用计算机的逻辑设计工具来测试逻辑电路功能和时序余量。

公开(公告)号：US20070225948A1

公开(公告)日：2007-09-27

申请号：US11587493

申请日：2005-04-28

申请人： Nobuhisa Takezawa ,  Kazumi Miyagi ,  Yuuji Uenohara ,  Masatoshi Kawashima ,  Masayuki Takayama ,  Hiroaki Okuda

发明人： Nobuhisa Takezawa ,  Kazumi Miyagi ,  Yuuji Uenohara ,  Masatoshi Kawashima ,  Masayuki Takayama ,  Hiroaki Okuda

IPC分类号： G06F15/00 ,  G06F11/34 ,  G06F17/50

CPC分类号： G06F17/50 ,  G06F2217/10 ,  G06Q10/06 ,  G06Q30/0283

摘要： Inputting data necessary for designing an IT system leads a throughput evaluation part to draft a system idea meeting a design standard value for throughput and leads a reliability evaluation part to draft the system idea meeting a design standard value for failure probability. A cost evaluation part evaluates a cost of the system idea, while a cost judgment part judges whether there exists a system idea whose cost evaluated by the cost evaluation part is within an allowable range or not. When the cost judgment part judges that there is no system idea, a reconfiguration part reconfigures the design standard value for throughput, the design standard value for failure probability, and the allowable range of cost in the input data part, and the reconfiguration part carries out calculations repeatedly until there can be drafted a system idea whose cost is within the allowable range.

摘要翻译： 输入IT系统设计所需的数据可以使吞吐量评估部分起草满足吞吐量设计标准值的系统思想，并引导可靠性评估部分起草满足故障概率设计标准值的系统思想。 成本评估部分评估系统思想的成本，而成本判断部分判断是否存在由成本评估部分评估的成本在可允许范围内的系统概念。 当成本判断部判断为没有系统思想时，重新配置部分重新配置吞吐量的设计标准值，故障概率的设计标准值和输入数据部分的成本允许范围，重新配置部分执行 反复计算，直到可以起草成本在允许范围内的系统想法。

公开(公告)号：US5420897A

公开(公告)日：1995-05-30

申请号：US97833

申请日：1993-07-29

申请人： Shigeo Kasai ,  Masatoshi Kawashima ,  Tsugio Yokoyama ,  Katsutada Aoki ,  Norihiko Handa ,  Megumu Yoshida ,  Morihiko Sato ,  Hiroshi Nakamura ,  Tohru Iijima ,  Junko Matsuda ,  Kenji Ogura ,  Makoto Ono ,  Sadao Hattori

发明人： Shigeo Kasai ,  Masatoshi Kawashima ,  Tsugio Yokoyama ,  Katsutada Aoki ,  Norihiko Handa ,  Megumu Yoshida ,  Morihiko Sato ,  Hiroshi Nakamura ,  Tohru Iijima ,  Junko Matsuda ,  Kenji Ogura ,  Makoto Ono ,  Sadao Hattori

IPC分类号： G21C1/02 ,  G21C7/28 ,  G21C11/08 ,  G21C15/10 ,  G21D3/10 ,  G21D3/16

CPC分类号： G21C1/02 ,  G21C11/08 ,  G21C15/10 ,  G21C7/28 ,  G21D3/10 ,  G21D3/16 ,  G21Y2002/30 ,  G21Y2002/401 ,  G21Y2004/30 ,  Y02E30/34 ,  Y02E30/39

摘要： A fast reactor comprises a core composed of nuclear fuel, a core barrel surrounding an outer periphery of the core, an annular reflector surrounding an outer periphery of the core barrel, a partition wall structure surrounding an outer periphery of the annular reflector and supporting the core barrel by a supporting structure arranged radially of the fast reactor, the partition wall structure constituting an inner wall of a coolant passage for a primary coolant, a neutron shield surrounding an outer periphery of the partition wall structure and disposed in the coolant passage, a reactor vessel surrounding an outer periphery of the neutron shield and having an inner wall constituting an outer wall of the coolant passage, and a guard vessel surrounding an outer periphery of the reactor vessel.

摘要翻译： 一种快速反应器包括由核燃料构成的核心，围绕核心外周的核心筒体，围绕核心筒体的外周的环形反射器，围绕环形反射器的外周并支撑芯体的分隔壁结构 通过在快速反应堆的径向配置的支撑结构，分隔壁结构构成用于主冷却剂的冷却剂通道的内壁，围绕分隔壁结构的外周并设置在冷却剂通道中的中子屏蔽，反应器 围绕中子屏蔽的外周并且具有构成冷却剂通道的外壁的内壁的容器以及围绕反应器容器的外周的保护容器。

公开(公告)号：US5196159A

公开(公告)日：1993-03-23

申请号：US735355

申请日：1991-07-24

申请人： Masatoshi Kawashima ,  Kazumi Miyagi ,  Masaaki Iida ,  Katutada Aoki ,  Norihiko Handa

发明人： Masatoshi Kawashima ,  Kazumi Miyagi ,  Masaaki Iida ,  Katutada Aoki ,  Norihiko Handa

IPC分类号： G21C1/02 ,  G21C7/28

CPC分类号： G21C1/02 ,  G21C7/28 ,  Y02E30/34 ,  Y02E30/39

摘要： A fast reactor comprises a reactor vessel to be arranged vertically in a reactor building, a reactor vessel upper structure disposed on an upper portion in the reactor vessel, a drum structure suspended from the reactor vessel structure into a central portion in the reactor vessel so as to define an annular portion between an outer periphery of the drum structure and an inner periphery of the reactor vessel, and a reactor core disposed in the drum structure. A reflector is disposed in the reactor vessel and is vertically movable along an outer periphery of the reactor core. The reflector may be composed of grain materials movable by gravity. An intermediate heat exchanger is further disposed at a portion above the reactor core and an electromagnetic pump is disposed in the reactor vessel for circulating coolant. The reactivity of the reactor core can be controlled by the reflector to thereby reduce the neutron irradiation amount to the reactor vessel.

摘要翻译： 快速反应器包括在反应堆建筑物中垂直布置的反应器容器，设置在反应器容器的上部的反应器容器上部结构，从反应器容器结构悬浮到反应器容器中的中心部分的鼓结构， 以限定在滚筒结构的外周和反应器容器的内周之间的环形部分，以及设置在滚筒结构中的反应堆芯。 反应器设置在反应堆容器中并且可沿反应堆芯的外周垂直移动。 反射器可以由重力移动的谷物材料组成。 中间热交换器还设置在反应堆堆芯上方的部分，电磁泵设置在反应器容器中用于循环冷却剂。 反应堆芯的反应性可以由反射器控制，从而减少反应堆容器的中子照射量。

公开(公告)号：US4766475A

公开(公告)日：1988-08-23

申请号：US946608

申请日：1986-12-29

申请人： Masatoshi Kawashima

发明人： Masatoshi Kawashima

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/11898 ,  H01L21/82 ,  H01L23/5286 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device which includes input and output buffers having a high versatility of design is disclosed. Each buffer provided in correspondence with a bonding pad is made usable for either the input buffer or the output buffer in accordance with a wiring pattern to be formed therein. With this arrangement, it is possible to use the same circuit elements for both the input buffer and the output buffer. Thus, circuit elements to be exclusively used for inputting and outputting respectively need not be separately formed, and the area occupied by the buffers is reduced to that extent, to realize an increase in the number of pins or a reduction in the size of a chip. In addition, since one buffer can be set for either inputting or outputting, enhancement in the versatility of the design of the pins or the chip is achieved.

摘要翻译： 公开了一种包括具有高通用性的输入和输出缓冲器的半导体集成电路器件。 根据要在其中形成的布线图案，可以将与焊盘对应地设置的每个缓冲器用于输入缓冲器或输出缓冲器。 通过这种布置，可以对输入缓冲器和输出缓冲器使用相同的电路元件。 因此，分别不需要分别形成专门用于输入和输出的电路元件，并且缓冲器占据的面积减小到这一程度，以实现引脚数量的增加或芯片尺寸的减小 。 此外，由于可以设置一个缓冲器用于输入或输出，所以实现了引脚或芯片的设计的多功能性的增强。

公开(公告)号：US08001059B2

公开(公告)日：2011-08-16

申请号：US11587493

申请日：2005-04-28

申请人： Nobuhisa Takezawa ,  Kazumi Miyagi ,  Yuuji Uenohara ,  Masatoshi Kawashima ,  Masayuki Takayama ,  Hiroaki Okuda

发明人： Nobuhisa Takezawa ,  Kazumi Miyagi ,  Yuuji Uenohara ,  Masatoshi Kawashima ,  Masayuki Takayama ,  Hiroaki Okuda

IPC分类号： G06F17/00

CPC分类号： G06F17/50 ,  G06F2217/10 ,  G06Q10/06 ,  G06Q30/0283

摘要： Inputting data necessary for designing an IT system leads a throughput evaluation part to draft a system idea meeting a design standard value for throughput and leads a reliability evaluation part to draft the system idea meeting a design standard value for failure probability. A cost evaluation part evaluates a cost of the system idea, while a cost judgment part judges whether there exists a system idea whose cost evaluated by the cost evaluation part is within an allowable range or not. When the cost judgment part judges that there is no system idea, a reconfiguration part reconfigures the design standard value for throughput, the design standard value for failure probability, and the allowable range of cost in the input data part, and the reconfiguration part carries out calculations repeatedly until there can be drafted a system idea whose cost is within the allowable range.

摘要翻译： 输入IT系统设计所需的数据可以使吞吐量评估部分起草满足吞吐量设计标准值的系统思想，并引导可靠性评估部分起草满足故障概率设计标准值的系统思想。 成本评估部分评估系统思想的成本，而成本判断部分判断是否存在由成本评估部分评估的成本在可允许范围内的系统概念。 当成本判断部判断为没有系统思想时，重新配置部分重新配置吞吐量的设计标准值，故障概率的设计标准值和输入数据部分的成本允许范围，重新配置部分执行 反复计算，直到可以起草成本在允许范围内的系统想法。

公开(公告)号：US07552076B1

公开(公告)日：2009-06-23

申请号：US09807963

申请日：2000-08-25

申请人： Yuji Uenohara ,  Ritsuo Yoshioka ,  Motohiko Onishi ,  Takahiro Tatsumi ,  Tadahiro Ohashi ,  Masatoshi Kawashima ,  Hiroaki Okuda

发明人： Yuji Uenohara ,  Ritsuo Yoshioka ,  Motohiko Onishi ,  Takahiro Tatsumi ,  Tadahiro Ohashi ,  Masatoshi Kawashima ,  Hiroaki Okuda

IPC分类号： G06Q40/00

CPC分类号： G06Q40/08 ,  G06Q40/06

摘要： A system for correctly evaluating price distribution and risk distribution for a financial product or its derivatives introduces a probability density function generated with a Boltzmann model at a higher accuracy than the Gaussian distribution for a probability density. The system has an initial value setup unit and an evaluation condition setup unit. Initial values include at least one of price, price change rate, and price change direction of a financial product. The evaluation conditions include at least time steps and a number of trials. A Boltzmann model analysis unit receives the initial values and the evaluation conditions, and repeats simulations of price fluctuation, based on the Boltzmann model using a Monte Carlo method. A velocity/direction distribution setup unit supplies probability distributions of the price, price change rate, and price change direction for the financial product to the Boltzmann model analysis unit. A random number generator for a Monte Carlo method is employed in the analysis by the Boltzmann model, and an output unit displays the analysis result. A dealing system applies the financial Boltzmann model to option pricing, and reproduces the characteristics of Leptokurcity and Fat-tail by a linear Boltzmann equation to define risk-neutral and unique probability measures. Consequently, option prices can be evaluated in a risk-neutral and unique manner, taking into account Leptokurcity and Fat-tail of a price change distribution.

摘要翻译： 正确评估金融产品或其衍生物的价格分布和风险分配的系统以概率密度高于高斯分布的准则，引入了用玻尔兹曼模型生成的概率密度函数。 系统具有初始值设定单元和评价条件设定单元。 初始值包括金融产品的价格，价格变动率和价格变动方向中的至少一个。 评估条件至少包括时间步骤和一些试验。 玻尔兹曼模型分析单元接收初始值和评估条件，并且基于使用蒙特卡罗方法的波尔兹曼模型重复价格波动的模拟。 速度/方向分布设置单元将金融产品的价格，价格变化率和价格变化方向的概率分布提供给玻尔兹曼模型分析单元。 在Boltzmann模型的分析中采用蒙特卡罗方法的随机数发生器，输出单元显示分析结果。 交易系统将金融玻尔兹曼模型应用于期权定价，并通过线性玻尔兹曼方程再现了Leptokurcity和Fat-tail的特征，以定义风险中立和独特的概率测度。 因此，期权价格可以以风险中立和独特的方式进行评估，同时考虑到价格变动分配的Leptokurcity和Fat-tail。

公开(公告)号：US20070198387A1

公开(公告)日：2007-08-23

申请号：US11733057

申请日：2007-04-09

申请人： Yuji Uenohara ,  Ritsuo Yoshioka ,  Motohiko Onishi ,  Takahiro Tatsumi ,  Tadahiro Ohashi ,  Masatoshi Kawashima ,  Hiroaki Okuda

发明人： Yuji Uenohara ,  Ritsuo Yoshioka ,  Motohiko Onishi ,  Takahiro Tatsumi ,  Tadahiro Ohashi ,  Masatoshi Kawashima ,  Hiroaki Okuda

IPC分类号： G06Q40/00

CPC分类号： G06Q40/08 ,  G06Q40/06

摘要： A system for correctly evaluating a price distribution and a risk distribution for a financial product or its derivatives introduces a probability density function generated with a Boltzmann model at a higher accuracy than the Gaussian distribution for a probability density. The system has an initial value setup unit and an evaluation condition setup unit. Initial values include at least one of price, price change rate, and the price change direction of a financial product. The evaluation conditions include at least time steps and the number of trials. The Boltzmann model analysis unit receives the initial values and the evaluation conditions, and repeats simulations of price fluctuation, based on the Boltzmann model using a Monte Carlo method. A velocity/direction distribution setup unit supplies the probability distributions of the price, price change rate, and the price change direction for the financial product to the Boltzmann model analysis unit. A random number generator for a Monte Carlo method employed in the analysis by the Boltzmann model, and an output unit displays the analysis result. A dealing system applies the financial Boltzmann model to option pricing, and reproduces the characteristics of Leptokurcity and Fat-tail by linear Boltzmann equation in order to define risk-neutral and unique probability measures. Consequently, option prices can be evaluated in a risk-neutral and unique manner, taking into account Leptokurcity and Fat-tail of a price change distribution.

摘要翻译： 用于正确评估金融产品或其衍生物的价格分布和风险分布的系统使用玻尔兹曼模型产生的概率密度函数以高于概率密度的高斯分布的精度引入。 系统具有初始值设定单元和评价条件设定单元。 初始值包括金融产品的价格，价格变动率和价格变动方向中的至少一个。 评估条件至少包括时间步骤和试验次数。 Boltzmann模型分析单元接收初始值和评估条件，并使用Monte Carlo方法基于Boltzmann模型重复价格波动的模拟。 速度/方向分布设置单元将金融产品的价格，价格变化率和价格变化方向的概率分布提供给玻尔兹曼模型分析单元。 用于通过玻尔兹曼模型分析的蒙特卡罗方法的随机数发生器和输出单元显示分析结果。 交易系统将金融玻尔兹曼模型应用于期权定价，并通过线性Boltzmann方程再现Leptokurcity和Fat-tail的特征，以定义风险中立和独特的概率测度。 因此，期权价格可以以风险中立和独特的方式进行评估，同时考虑到价格变动分配的Leptokurcity和Fat-tail。

公开(公告)号：US20050138666A1

公开(公告)日：2005-06-23

申请号：US10991823

申请日：2004-11-17

申请人： Sadayuki Narusawa ,  Tetsuya Matsuyama ,  Masatoshi Kawashima ,  Hiroaki Furuta ,  Katsuaki Tanaka ,  Yasuhiro Matsunuma

发明人： Sadayuki Narusawa ,  Tetsuya Matsuyama ,  Masatoshi Kawashima ,  Hiroaki Furuta ,  Katsuaki Tanaka ,  Yasuhiro Matsunuma

IPC分类号： G10K15/02 ,  H04L29/06 ,  H04N7/16 ,  H04N7/173 ,  H04N7/64

CPC分类号： H04L65/1006 ,  H04L29/06027

摘要： A data reproducing system includes: a receiver that receives streaming data via a network; a buffering device that buffers the received data; a reproducing unit that reproduces the data by reading the data from the buffering device; and a controller that controls a reproducing speed of the reproducing unit in response to excess and deficiency of an amount of buffer from a predetermined target value to maintain the amount of buffer of the buffering device at the target value.

摘要翻译： 数据再现系统包括：经由网络接收流数据的接收器; 缓冲装置，缓冲所接收的数据; 再现单元，通过从缓冲装置读取数据再现数据; 以及控制器，其响应于来自预定目标值的缓冲器的量的过量和不足而控制再现单元的再现速度，以将缓冲装置的缓冲器的量保持在目标值。