公开(公告)号：US4744063A

公开(公告)日：1988-05-10

申请号：US613614

申请日：1984-05-24

申请人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

发明人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/418 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C8/18

摘要： A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

摘要翻译： 静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。 当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。 该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

公开(公告)号：US4730279A

公开(公告)日：1988-03-08

申请号：US842441

申请日：1986-03-21

申请人： Takayuki Ohtani

发明人： Takayuki Ohtani

IPC分类号： G11C8/18 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C8/18 ,  G11C11/419

摘要： A memory cell array consists of a plurality of memory sections. A pair of bit lines are provided for each column, and word lines are provided each for each row in each memory section. One end of the current path of a first transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. One end of the current path of a second transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. The current capacity of the first transistor is larger than that of the second transistor. After an address signal varies and a predetermined period elapses, the first transistor in the selected section turns on, the second transistor in the selected section turns off, the first transistor in the nonselected section turns off, and the second transistors in the nonselected section turns on. The bit lines in the selected section are charged for a predetermined period of time after the address signal changes, to pull up the voltages of the bit lines in the nonselected section to a power supply voltage. A row decoder renders the word line active in level after the first transistor connected to the bit lines of the selected section is turned off according to an address signal.

摘要翻译： 存储单元阵列由多个存储器部分组成。 为每列提供一对位线，并且为每个存储器部分中的每行提供字线。 第一晶体管的电流路径的一端连接到对应的位线。 预定的电压被施加到第一晶体管的电流路径的另一端。 第二晶体管的电流路径的一端连接到对应的位线。 预定的电压被施加到第一晶体管的电流路径的另一端。 第一晶体管的电流容量大于第二晶体管的电流容量。 在地址信号变化并且经过预定时间后，所选择的部分中的第一晶体管导通，所选择的部分中的第二晶体管截止，非选择部分中的第一晶体管截止，并且非选择部分中的第二晶体管转向 上。 所选择的部分中的位线在地址信号改变之后的预定时间段内被充电，以将非选择部分中的位线的电压上拉到电源电压。 根据地址信号，在连接到所选择部分的位线的第一晶体管截止之后，行解码器使字线有效。

公开(公告)号：US5607595A

公开(公告)日：1997-03-04

申请号：US338493

申请日：1994-12-20

申请人： Masami Hiasa ,  Nobuyuki Ashie ,  Susumu Saito ,  Takayuki Ohtani

发明人： Masami Hiasa ,  Nobuyuki Ashie ,  Susumu Saito ,  Takayuki Ohtani

IPC分类号： B01D15/00 ,  B01J20/34 ,  C02F1/00 ,  C02F1/28 ,  C02F1/76

CPC分类号： C02F1/766 ,  B01J20/20 ,  B01J20/28023 ,  B01J20/28078 ,  B01J20/2809 ,  B01J20/3416 ,  B01J20/3483 ,  C02F1/003 ,  C02F1/283 ,  B01J2220/62

摘要： A process and device for purifying water of the type wherein activated carbon is subjected to regeneration. Tap water is contacted with activated carbon fibers characterized by a narrow micropore distribution and a high adsorption speed, to eliminate by adsorption residual chlorine, harmful trihalomethane compounds and smelly substances such as 2-methylisoborneol and geosmin that are present in tap water. Activated carbon fibers having a modal micropore diameter of about 1.8-3.0 nm, preferably, 2.0-2.7 nm, are used to cause the large-molecular-weight smelly substances to be intensively and selectively adsorbed by the activated carbon fibers. In non-use, the activated carbon fibers are occasionally heated at a temperature of 100.degree.-120.degree. C. whereby trihalomethane compounds adsorbed in the activated carbon fibers are desorbed so that the adsorption capability of activated carbon fibers with respect to trihalomethanes is restored. Accordingly, trihalomethanes as well as smelly substances can be eliminated for a long period without requiring replacement of activated carbon fiber cartridge, while using a limited amount of activated carbon fibers.

摘要翻译： PCT No.PCT / JP94 / 00518 Sec。 371日期1994年12月20日第 102（e）日期1994年12月20日PCT 1994年3月30日PCT公布。 公开号WO95 / 00442 日期1995年1月5日一种用于净化活性炭再生的类型的水的方法和装置。 自来水与活性炭纤维接触，其特征在于窄的微孔分布和高吸附速度，通过吸附剩余的氯，有害的三卤代甲烷化合物和自来水中存在的2-甲基异山梨醇和地塞米松等有害物质来消除。 使用具有约1.8-3.0nm的模态微孔直径，优选为2.0-2.7nm的活性碳纤维，使大分子量臭味物质被活性炭纤维集中和选择性地吸附。 在不使用时，活性碳纤维偶尔在100-120℃的温度下加热，由此吸附在活性碳纤维中的三卤代甲烷化合物被解吸，从而恢复活性炭纤维相对于三卤甲烷的吸附能力。 因此，在使用有限量的活性炭纤维的同时，可以长时间地消除三卤甲烷和臭味物质，而不需要更换活性炭纤维筒。

公开(公告)号：US4882708A

公开(公告)日：1989-11-21

申请号：US145411

申请日：1988-01-19

申请人： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

发明人： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

IPC分类号： G11C11/41 ,  G11C11/419

CPC分类号： G11C11/419

摘要： A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.

摘要翻译： 一方面，位线之间和另一方的电源电位之间设置预充电电路。 通过清除信号将预充电电路控制为导通/不导通。 还提供控制单元，当提供清除信号时，控制解码器，以将所有字线设置为选择状态。 在清除模式下，写入电路将同一数据同时写入所有存储单元。

公开(公告)号：US4881202A

公开(公告)日：1989-11-14

申请号：US138800

申请日：1987-12-29

申请人： Jun-ichi Tsujimoto ,  Masataka Matsui ,  Hiroshi Iwai ,  Takayuki Ohtani

发明人： Jun-ichi Tsujimoto ,  Masataka Matsui ,  Hiroshi Iwai ,  Takayuki Ohtani

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/802 ,  G11C29/844

摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.

公开(公告)号：US4594519A

公开(公告)日：1986-06-10

申请号：US534691

申请日：1983-09-22

申请人： Takayuki Ohtani ,  Tetsuya Iizuka

发明人： Takayuki Ohtani ,  Tetsuya Iizuka

IPC分类号： H03K19/20 ,  G11C8/00 ,  H03K19/00 ,  H03K19/094 ,  H03K19/003

CPC分类号： H03K19/09425 ,  H03K19/09429

摘要： A signal input circuit particularly well suited for use in MOS integrated circuits. The signal input circuit includes: and input gate circuit for receiving an input signal and an enable control signal, and for generating an output signal equal to the input signal when the enable control signal is in an "enable" state, and for providing a high output impedance when the enable control signal is in a "disable" state; and a holding circuit coupled to an output of the input gate circuit and to receiving the enable control signal, for holding, during the disable state, the output state of the input gate circuit immediately before the enable control signal changes to a disable state, the output impedance being high when the enable control signal is in an enable state.

摘要翻译： 特别适用于MOS集成电路的信号输入电路。 信号输入电路包括：输入门电路，用于接收输入信号和使能控制信号，并且在使能控制信号处于“使能”状态时，产生等于输入信号的输出信号，并提供高电平 当使能控制信号处于“禁止”状态时的输出阻抗; 以及保持电路，其耦合到所述输入门电路的输出并且接收所述使能控制信号，以在所述禁止状态期间保持所述输入门电路的输出状态，所述输入门电路在所述使能控制信号变为禁用状态之前， 当使能控制信号处于使能状态时，输出阻抗为高。

公开(公告)号：US4587638A

公开(公告)日：1986-05-06

申请号：US630115

申请日：1984-07-12

申请人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

发明人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

IPC分类号： G11C29/00 ,  G11C7/02

CPC分类号： G11C29/84 ,  G11C29/832

摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

摘要翻译： 在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。 当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。 连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。 因此，不选择具有缺陷部分的存储单元。

公开(公告)号：US4563593A

公开(公告)日：1986-01-07

申请号：US538277

申请日：1983-10-03

申请人： Mitsuo Isobe ,  Takayuki Ohtani

发明人： Mitsuo Isobe ,  Takayuki Ohtani

IPC分类号： H03K5/1532 ,  H03K3/02 ,  H03K5/1534 ,  H03K5/153

CPC分类号： H03K5/1534 ,  H03K3/02

摘要： A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal. The transition detector circuit further comprises a first switching circuit which turns on or off in response to a signal fed from the third invertor train to produce a pulse signal having a first delay time determined by the first and third invertor trains, and a second switching circuit which turns on or off in response to a signal fed from the fourth invertor train and turns off or on in response to a signal fed from the fifth invertor train to produce a pulse signal having a second delay time determined by the second, fourth and fifth invertor trains.

摘要翻译： 一个转换检测器电路包括一个包括2n级反相器（n：包括零的正整数）的第一个反相器列，其输入连接到一个信号输入端，同时其输出连接到一个同相输出端，一个第二反相器 其包括2n + 1级的反相器，其输入连接到信号输入端，而其输出连接到反相输出端，第三反相器列，包括至少一级的反相器，其连接到反相器 第一反相器列车的输出，第四反相器列车，包括连接到第二逆变器列车的输出端的反相器的至少一级，以及包括连接到第二逆变器列的至少一级的逆变器列 到信号输入端子。 转换检测器电路还包括第一开关电路，其响应于从第三反相器序列馈送的信号而导通或截止以产生具有由第一和第三反相器列车确定的第一延迟时间的脉冲信号，以及第二开关电路 其响应于从第四反相器列车馈送的信号而接通或断开，并且响应于从第五反相器列车馈送的信号而断开或接通，以产生具有由第二，第四和第五变换器确定的第二延迟时间的脉冲信号 倒车火车