公开(公告)号：US4882708A

公开(公告)日：1989-11-21

申请号：US145411

申请日：1988-01-19

申请人： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

发明人： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

IPC分类号： G11C11/41 ,  G11C11/419

CPC分类号： G11C11/419

摘要： A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.

摘要翻译： 一方面，位线之间和另一方的电源电位之间设置预充电电路。 通过清除信号将预充电电路控制为导通/不导通。 还提供控制单元，当提供清除信号时，控制解码器，以将所有字线设置为选择状态。 在清除模式下，写入电路将同一数据同时写入所有存储单元。

公开(公告)号：US4813022A

公开(公告)日：1989-03-14

申请号：US136769

申请日：1987-12-22

申请人： Masataka Matsui ,  Tetsuya Iizuka ,  Jun-ichi Tsujimoto ,  Takayuki Ohtani ,  Mitsuo Isobe

发明人： Masataka Matsui ,  Tetsuya Iizuka ,  Jun-ichi Tsujimoto ,  Takayuki Ohtani ,  Mitsuo Isobe

IPC分类号： G11C11/417 ,  G11C7/12 ,  G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C7/12 ,  G11C11/419

摘要： The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.

摘要翻译： 位线的每个充电/均衡MOS晶体管的阈值电压小于通常的ON型位线上拉晶体管的阈值电压。 通过这一功能，在读出操作期间，没有电流从电源VDD流过位线。 可以高速地增加一对位线之间的电压差，从而增加读出速度。

公开(公告)号：US4697112A

公开(公告)日：1987-09-29

申请号：US878372

申请日：1986-06-25

申请人： Takayuki Ohtani ,  Mitsuo Isobe ,  Akira Aono ,  Nobuaki Urakawa

发明人： Takayuki Ohtani ,  Mitsuo Isobe ,  Akira Aono ,  Nobuaki Urakawa

IPC分类号： H03K5/02 ,  G11C11/409 ,  G11C11/419 ,  H03F3/45 ,  H03K3/356

CPC分类号： H03F3/45183 ,  H03K3/356104 ,  H03F2203/45394 ,  H03F2203/45466 ,  H03F2203/45644 ,  H03F2203/45674 ,  H03F2203/45726

摘要： There is disclosed a sense amplifier characterized by comprising a pull-up circuit. The pull-up circuit comprises a first transistor arranged between the first of a pair of output nodes and a pull-up power source potential node, and a second transistor arranged between the second of the pair of output nodes and the pull-up power source potential node. The gate of the first transistor is connected to the second output node and the gate of the second transistor is connected to the first output node.

摘要翻译： 公开了一种感测放大器，其特征在于包括一个上拉电路。 上拉电路包括布置在一对输出节点之间的第一个和上拉电源电势节点之间的第一晶体管，以及布置在该对输出节点中的第二个和上拉电源之间的第二晶体管 潜在节点。 第一晶体管的栅极连接到第二输出节点，第二晶体管的栅极连接到第一输出节点。

公开(公告)号：US4744063A

公开(公告)日：1988-05-10

申请号：US613614

申请日：1984-05-24

申请人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

发明人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/418 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C8/18

摘要： A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

摘要翻译： 静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。 当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。 该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

公开(公告)号：US4982365A

公开(公告)日：1991-01-01

申请号：US476137

申请日：1990-02-07

申请人： Takayuki Ohtani ,  Mitsuo Isobe

发明人： Takayuki Ohtani ,  Mitsuo Isobe

IPC分类号： G11C11/41 ,  G11C7/20 ,  G11C11/401 ,  G11C11/419

CPC分类号： G11C7/20 ,  G11C11/419

摘要： During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.

摘要翻译： 在数据清除操作期间，在保持关断状态下，与至少一列相关联的每个静态型存储单元中的传输栅极晶体管，并入存储单元中的两个驱动晶体管中的一个的源极被设置为高 电位电平，另一个驱动晶体管的源极为低电平。 结果，在存储单元矩阵中执行清零操作至少为1列。 由于存储器件的布置，在清除操作期间不需要地址选择操作来选择存储器单元。 此外，清除操作以存储单元矩阵中的1列的最小单位进行。 因此，清除操作的处理时间减少。 此外，由于在清除动作期间存储单元中的传输栅极晶体管保持在截止状态，所以清除操作期间流过的直流电流减小，结果是功耗降低。

公开(公告)号：US4587638A

公开(公告)日：1986-05-06

申请号：US630115

申请日：1984-07-12

申请人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

发明人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

IPC分类号： G11C29/00 ,  G11C7/02

CPC分类号： G11C29/84 ,  G11C29/832

摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

摘要翻译： 在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。 当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。 连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。 因此，不选择具有缺陷部分的存储单元。

公开(公告)号：US4563593A

公开(公告)日：1986-01-07

申请号：US538277

申请日：1983-10-03

申请人： Mitsuo Isobe ,  Takayuki Ohtani

发明人： Mitsuo Isobe ,  Takayuki Ohtani

IPC分类号： H03K5/1532 ,  H03K3/02 ,  H03K5/1534 ,  H03K5/153

CPC分类号： H03K5/1534 ,  H03K3/02

摘要： A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal. The transition detector circuit further comprises a first switching circuit which turns on or off in response to a signal fed from the third invertor train to produce a pulse signal having a first delay time determined by the first and third invertor trains, and a second switching circuit which turns on or off in response to a signal fed from the fourth invertor train and turns off or on in response to a signal fed from the fifth invertor train to produce a pulse signal having a second delay time determined by the second, fourth and fifth invertor trains.

摘要翻译： 一个转换检测器电路包括一个包括2n级反相器（n：包括零的正整数）的第一个反相器列，其输入连接到一个信号输入端，同时其输出连接到一个同相输出端，一个第二反相器 其包括2n + 1级的反相器，其输入连接到信号输入端，而其输出连接到反相输出端，第三反相器列，包括至少一级的反相器，其连接到反相器 第一反相器列车的输出，第四反相器列车，包括连接到第二逆变器列车的输出端的反相器的至少一级，以及包括连接到第二逆变器列的至少一级的逆变器列 到信号输入端子。 转换检测器电路还包括第一开关电路，其响应于从第三反相器序列馈送的信号而导通或截止以产生具有由第一和第三反相器列车确定的第一延迟时间的脉冲信号，以及第二开关电路 其响应于从第四反相器列车馈送的信号而接通或断开，并且响应于从第五反相器列车馈送的信号而断开或接通，以产生具有由第二，第四和第五变换器确定的第二延迟时间的脉冲信号 倒车火车

公开(公告)号：US09074575B2

公开(公告)日：2015-07-07

申请号：US13157760

申请日：2011-06-10

申请人： Takayuki Sakurai ,  Takayuki Ohtani

发明人： Takayuki Sakurai ,  Takayuki Ohtani

IPC分类号： F23Q7/00 ,  F23Q13/00 ,  F02P19/02 ,  F02D41/24

CPC分类号： F02P19/025 ,  F02D41/2432 ,  F02D41/2464 ,  F02P19/027

摘要： A GCU (21) includes calibration means (33) which supplies electric current to a glow plug (1) when an internal combustion engine EN to which the glow plug (1) is attached is stopped, to thereby obtain a pre-correction target resistance of the glow plug (1). The calibration means (33) supplies a predetermined first electric power to the glow plug (1) in a predetermined first energization period, and supplies a predetermined second electric power to the glow plug (1) after the first energization period. The second electric power is set such that, when the second electric power is supplied to the glow plug (1) and the temperature of the glow plug (1) becomes saturated, the temperature of the glow plug (1) becomes equal to the target temperature. Further, the first electric power is greater than the second electric power.

摘要翻译： GCU（21）包括当安装了电热塞（1）的内燃机EN停止时向电热塞（1）供应电流的校准装置（33），从而获得预校正目标电阻 的电热塞（1）。 校准装置（33）在预定的第一通电时段内向预热塞（1）提供预定的第一电力，并且在第一通电时段之后向预热塞（1）提供预定的第二电力。 第二电力被设定为使得当第二电力被提供给电热塞（1）并且电热塞（1）的温度饱和时，电热塞（1）的温度变得等于目标 温度。 此外，第一电力大于第二电力。

公开(公告)号：US08423197B2

公开(公告)日：2013-04-16

申请号：US12623812

申请日：2009-11-23

申请人： Takayuki Sakurai ,  Takayuki Ohtani ,  Hiroki Tsuchiya

发明人： Takayuki Sakurai ,  Takayuki Ohtani ,  Hiroki Tsuchiya

IPC分类号： G05D23/19

CPC分类号： F02P19/025 ,  F02D41/042 ,  F02D41/2464 ,  F02P19/027

摘要： A heater energization control apparatus. When an engine is stopped, a microcomputer of a GCU enters a power save mode. When the microcomputer returns to a normal mode in response to an interruption signal periodically generated from an interruption timer, the microcomputer supplies electricity to a heating resistor for a short time and obtains its resistance (S19). When the resistance is greater than a first reference value, the microcomputer determines that a glow plug is removed from the engine; that is, the glow plug is being exchanged (S29). The microcomputer sets an exchange flag to “1” (S30), and performs calibration for the heating resistor of a new glow plug after the engine is operated next time (S35). When the current resistance becomes smaller than the past resistance, the microcomputer determines that the glow plug has been exchanged.

摘要翻译： 一种加热器通电控制装置。 当发动机停止时，GCU的微型计算机进入省电模式。 当微计算机响应于从中断定时器周期性地产生的中断信号而返回到正常模式时，微计算机在短时间内向加热电阻器供电并获得其电阻（S19）。 当电阻大于第一参考值时，微型计算机确定从发动机移除电热塞; 也就是说，正在更换电热塞（S29）。 微型计算机将交换标志设置为1（S30），并且在发动机下一次操作之后对新的电热塞的加热电阻器进行校准（S35）。 当电流电阻变得小于过去电阻时，微机确定电热塞已被更换。

公开(公告)号：US4815040A

公开(公告)日：1989-03-21

申请号：US100640

申请日：1987-09-24

申请人： Masataka Matsui ,  Takayuki Ohtani

发明人： Masataka Matsui ,  Takayuki Ohtani

IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419

摘要： In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.

摘要翻译： 在选定的列中，不选择上拉晶体管对，而是选择传输栅极晶体管对。 在读取模式下，传输栅极晶体管对用作位线对之间的上拉负载。 然而，传输栅极晶体管对保持截止，直到位线对上的电压从电源电位电平降低到传输栅极晶体管的阈值电压电平。 因此，当位线对上的电压在等于电源电位电平的电压到低于电源电位的电位的范围内时，在位线对中不形成直流电流路径， 阈值电压电平，并且位线对上的电位差的增加速率由存储单元的引入电流决定。 因此，可以实现高速感测操作。 在写入模式下，传输栅极晶体管对用于位线上拉功能。 由于没有布置正常导通的位线负载晶体管，所以不存在包括位线对的直流电路，因此可以实现低功耗。