公开(公告)号：US06326826B1

公开(公告)日：2001-12-04

申请号：US09574571

申请日：2000-05-17

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L700

CPC分类号： H03L7/087 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/10 ,  H03L2207/14

摘要： A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.

摘要翻译： 描述了包括频率检测逻辑和相位检测器的延迟锁定环（DLL），其具有与常规电荷泵锁相环一样​​宽的操作范围。 频率检测器逻辑计算在参考时钟的一个周期期间从参考时钟产生的多相时钟的上升沿的数量。 环路滤波器用于调整每个多相时钟的频率，直到通过比较上升沿的数量获得频率锁定为止。 在频率锁定之后，相位检测逻辑用于微调剩余的相位误差。

公开(公告)号：US06756828B2

公开(公告)日：2004-06-29

申请号：US10196479

申请日：2002-07-17

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L706

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

摘要： A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

摘要翻译： 提供了一种锁相环（PLL）及其使用方法，包括多反馈CMOS压控振荡器（VCO）和多相采样分数N预分频器。 PLL为单芯片CMOS射频（RF）通信系统提供了更高的性能特性。 多反馈CMOS VCO在降低VCO信号的上升/下降时间的同时保持VCO信号的幅度。 多反馈CMOS VCO进一步降低了电源噪声影响。 多相采样分数N预分频器为CMOS VCO提供足够的带宽，同时保持光谱纯度并减少分数。 多相采样分数N预分频器可以包括分频器，采样器电路，选择器电路和模块化计数器。

公开(公告)号：US06538498B2

公开(公告)日：2003-03-25

申请号：US10113600

申请日：2002-04-02

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03K500

CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

摘要： A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

公开(公告)号：US06510185B2

公开(公告)日：2003-01-21

申请号：US09897975

申请日：2001-07-05

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03D324

CPC分类号： H03H11/22 ,  H03D7/1441 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/403

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

公开(公告)号：US06424192B1

公开(公告)日：2002-07-23

申请号：US09709311

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L706

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

摘要： A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

公开(公告)号：US06404277B1

公开(公告)日：2002-06-11

申请号：US09709310

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03K501

CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

摘要： A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

公开(公告)号：US08289314B2

公开(公告)日：2012-10-16

申请号：US12569186

申请日：2009-09-29

申请人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

发明人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

IPC分类号： G06F3/038 ,  G11B7/00

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2370/08 ,  H03K7/04

摘要： A method of modulating and demodulating a signal includes modulating data information included in an input data signal provided from an external source and clock information included in an input clock signal provided from the external source into a transmission signal, using (n+1) delay clock signals generated based on the input clock signal, where n is a natural number. The transmission signal is demodulated into an output clock signal including restored clock information and an output data signal including restored data information, using (m+1) delay clock signals generated based on the clock information, where m is a natural number less than n.

摘要翻译： 调制和解调信号的方法包括：使用（n + 1）个延迟时钟将从外部源提供的输入数据信号中包括的数据信息和从外部源提供的输入时钟信号中包括的时钟信息调制成发送信号 基于输入时钟信号生成的信号，其中n是自然数。 使用基于时钟信息生成的（m + 1）个延迟时钟信号，将发送信号解调为包括恢复的时钟信息的输出时钟信号和包括恢复的数据信息的输出数据信号，其中m是小于n的自然数。

公开(公告)号：US20120206176A1

公开(公告)日：2012-08-16

申请号：US13398245

申请日：2012-02-16

申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

IPC分类号： H03L7/08

CPC分类号： H03L7/0812 ,  H03L7/095 ,  H03L7/101

摘要： A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.

摘要翻译： 公开了一种粗锁检测器。 课程锁定检测器使用初始锁定范围来确定课程锁定，并且一旦达到课程锁定，则使用修改的锁定范围来确定课程锁定。

公开(公告)号：US20090219739A1

公开(公告)日：2009-09-03

申请号：US12223552

申请日：2006-09-15

申请人： Young-Deok Kim ,  Deog-Kyoon Jeong

发明人： Young-Deok Kim ,  Deog-Kyoon Jeong

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell (100); a first comparator (110) connected to the memory cell; a second comparator (120) connected to the first comparator, a ground voltage and a predetermined voltage. The comparators conduct a comparing operation in responsive to operator data. Instead of the conventional TCAMs employing 0, 1, and X (don't care) bit, a CAM utilizing the RMC can conduct a comparing operation with less memory by storing the operator data 0 and 1 in advance. Accordingly, memory-use efficiency can be increased.

摘要翻译： 范围匹配单元（RMC）包括位线（BL）; 字线（WL）; 匹配线（ML）; 搜索行（SL）; 存储单元（100）; 连接到所述存储单元的第一比较器（110） 连接到第一比较器的第二比较器（120），接地电压和预定电压。 比较器根据操作员数据进行比较操作。 代替采用0，1和X（无关）位的常规TCAM，使用RMC的CAM可以通过预先存储操作数据0和1来进行具有较少存储器的比较操作。 因此，可以提高记忆使用效率。

公开(公告)号：US07551909B1

公开(公告)日：2009-06-23

申请号：US10651500

申请日：2003-08-29

申请人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

发明人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

IPC分类号： H04B1/06

CPC分类号： H03L7/107 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995

摘要： A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-μm CMOS technology, and shows 10−12 bit error rate up to speeds of 3 Gbps.

摘要翻译： 双电流通道压控振荡器既保留了无缝频率采集和均匀的VCO增益降低，​​又保留了原始工作范围和锁相环特性。 本发明提供了一种四通道收发器，包括一个锁相环电路，该锁相环电路包括用于产生时钟信号的压控振荡器，用于存储要发送的数据的FIFO缓冲器，用于将参考时钟与所产生的时钟进行比较的频率比较器 来自锁相环电路的信号; 以及包含在压控振荡器内的折叠饥饿逆变器电路，其中折叠的饥饿逆变器提供两个电流路径。 双电流路径允许同步粗略和精细的相位跟踪。 凭借这种低抖动性能和广泛的工作范围，四通道收发器可以以0.18微米CMOS技术实现，并显示出10到12位的误码率，达到3 Gbps的速度。