公开(公告)号：US20150070909A1

公开(公告)日：2015-03-12

申请号：US14482466

申请日：2014-09-10

Applicant: LG INNOTEK CO., LTD.

Inventor： Kyeoung An JUNG ,  Jung Hun OH

IPC: H01L33/48 ,  F21V29/00 ,  F21V3/04 ,  F21V3/00

CPC classification number: H01L33/48 ,  F21V3/00 ,  F21V3/10 ,  F21V29/70 ,  F21Y2101/00 ,  F21Y2115/10 ,  H01L33/486 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A light emitting device package includes a package body, and a light emitting device chip provided on a chip mount area of the package body. A molding member is provided on the package body. The package body includes a central area having the chip mount area and a chip non-mount area adjacent to the chip mount area. An upper surface of the light emitting device chip is higher than an upper surface of the package body in the chip non-mount area and an upper surface of the package body in the peripheral area.

Abstract translation: 发光器件封装包括封装体，以及设置在封装体的芯片安装区域上的发光器件芯片。 成型构件设置在包装体上。 封装体包括具有芯片安装区域的中心区域和与芯片安装区域相邻的芯片非安装区域。 发光器件芯片的上表面高于芯片非安装区域中的封装体的上表面和周边区域中的封装体的上表面。

公开(公告)号：US20140124836A1

公开(公告)日：2014-05-08

申请号：US13796688

申请日：2013-03-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Jung Hun OH

IPC: H01L29/778

CPC classification number: H01L29/0646 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/34 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer, a gate electrode disposed on the portion of the second semiconductor layer exposed via the third semiconductor layer, and a source electrode and a drain electrode disposed on the third semiconductor layer at both sides of the gate electrode to be spaced apart from each other. An electrical segregation region is formed in the third semiconductor layer between the gate electrode and the drain electrode.

Abstract translation: 公开了功率半导体器件。 功率半导体器件包括衬底，设置在衬底上的第一半导体层，设置在第一半导体层上的第二半导体层，设置在第二半导体层上并暴露第二半导体层的一部分的第三半导体层，栅极 设置在经由第三半导体层露出的第二半导体层的部分上的电极以及设置在栅电极两侧彼此间隔开的第三半导体层上的源电极和漏电极。 在栅电极和漏电极之间的第三半导体层中形成电偏析区域。