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    Threshold Acquisition and Adaption in NAND Flash Memory
    16.
    发明申请
    Threshold Acquisition and Adaption in NAND Flash Memory 有权
    NAND闪存中的阈值采集和适配

    公开(公告)号：US20140119113A1

    公开(公告)日：2014-05-01

    申请号：US13664583

    申请日：2012-10-31

    Applicant: LSI CORPORATION

    Inventor： Haitao Xia ,  Fan Zhang ,  Ming Jin ,  Shaohua Yang

    IPC: G11C16/06

    CPC classification number: G11C16/06 ,  G11C16/34 ,  G11C16/349

    Abstract: A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration.

    Abstract translation: 一种用于获取和跟踪至少一个闪存芯片的至少一个单元的至少一个阈值电压的方法，装置和控制器。 该方法可以包括获取至少一个闪存单元的特定单元的至少一个阈值电压。 该方法还可以包括执行至少一个阈值电压调整迭代。

    Systems and Methods for Indirect Information Assisted Media Defect Scan
    17.
    发明申请
    Systems and Methods for Indirect Information Assisted Media Defect Scan 审中-公开
    间接信息辅助媒体缺陷扫描的系统和方法

    公开(公告)号：US20140108875A1

    公开(公告)日：2014-04-17

    申请号：US13652046

    申请日：2012-10-15

    Applicant: LSI CORPORATION

    Inventor： Ming Jin ,  Fan Zhang ,  Haitao Xia

    IPC: G11B20/18 ,  G06F11/16

    CPC classification number: G11B20/18

    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for media defect detection.

    Abstract translation: 与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于介质缺陷检测的系统和方法。

    ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES
    19.
    发明申请
    ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES 有权
    使用转换型低密度密度检查代码对闪存中的编码和解码

    公开(公告)号：US20130145238A1

    公开(公告)日：2013-06-06

    申请号：US13755676

    申请日：2013-01-31

    Applicant: LSI Corporation

    Inventor： Abdel Hakim S. Alhussien ,  Erich F. Haratsch ,  Zongwang Li ,  Fan Zhang

    IPC: H03M13/23

    CPC classification number: H03M13/23 ,  G06F11/1072 ,  H03M13/1154 ,  H03M13/6325

    Abstract: Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline.

    Abstract translation: 提供了使用卷积型低奇偶校验密码校验码来对闪速存储器进行编码和解码的方法和装置。 使用诸如空间耦合的低密度奇偶校验码的卷积型低密度奇偶校验码对要存储在闪速存储器件上的多个比特进行编码。 编码的页面或其部分可以独立于其他页面被解码。 在一个实施例中，编码页面与同一字线或不同字线中的一个或多个附加页面联合解码。

    Low density parity check decoder with dynamic scaling
    20.
    发明授权
    Low density parity check decoder with dynamic scaling 有权
    低密度奇偶校验解码器，动态缩放

    公开(公告)号：US09130589B2

    公开(公告)日：2015-09-08

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: G11B20/18 ,  H03M13/13 ,  H03M13/11 ,  H03M13/00 ,  H03M13/27

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

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