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29 条记录 (耗时 0.027 秒)

    Method for incorporating pattern dependent effects in circuit simulations
    12.
    发明申请
    Method for incorporating pattern dependent effects in circuit simulations 有权

    公开(公告)号：US20060190854A1

    公开(公告)日：2006-08-24

    申请号：US11043609

    申请日：2005-01-24

    申请人： Jeffrey Watt

    发明人： Jeffrey Watt

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

    Electrostatic discharge (ESD) protection circuit and structure for output drivers
    13.
    发明授权
    Electrostatic discharge (ESD) protection circuit and structure for output drivers 失效
    静电放电（ESD）保护电路和输出驱动器结构

    公开(公告)号：US5623156A

    公开(公告)日：1997-04-22

    申请号：US535426

    申请日：1995-09-28

    申请人： Jeffrey Watt

    发明人： Jeffrey Watt

    IPC分类号： H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0251

    摘要： An integrated circuit device includes internal power supply buses V.sub.SSI, and V.sub.DDI, and output power supply buses V.sub.SSO, and V.sub.DDO. An output driver of the device has an active p-channel pull up, and n-channel pulldown complementary pair configuration with their outputs tied to a common node, which is in turn tied to an I/O pad. A protection circuit for protecting the device from ESD events includes a series resistor disposed between the source of the n-channel pulldown transistor, and power supply bus V.sub.SSO. The protection circuitry includes a diode having its cathode connected to the I/O pad, and its anode connected to power supply bus V.sub.SSI. The pulldown transistor includes an n.sup.+ drain region, which is shared with the diode, wherein the diode and transistor are merged. The resistor between the pulldown transistor source, and power supply V.sub.SSO permits maintaining this merged structure. In an alternate embodiment, an n-well may be formed to underlie the p.sup.+ anode of the diode, and wholly surround it. The n-well extends toward and contacts the n.sup.+ drain region of the pulldown FET. The n-well isolates the p.sup.+ region from the substrate, permitting the p.sup.+ region to be connected to the power supply bus V.sub.SSO thereby eliminating the requirement that a metal power supply bus V.sub.SSI be routed into the I/O portion of the device.

    摘要翻译： 集成电路器件包括内部电源总线VSSI和VDDI，以及输出电源总线VSSO和VDDO。 该器件的输出驱动器具有有源p沟道上拉和n沟道下拉互补配置，其输出端连接到公共节点，该公共节点又连接到I / O焊盘。 用于保护器件免受ESD事件的保护电路包括设置在n沟道下拉晶体管的源极和电源总线VSSO之间的串联电阻器。 保护电路包括二极管，其二极管的阴极连接到I / O焊盘，其阳极连接到电源总线VSSI。 下拉晶体管包括与二极管共享的n +漏极区，其中二极管和晶体管被合并。 下拉晶体管源和电源VSSO之间的电阻允许维持这种合并结构。 在替代实施例中，可以形成n阱以将二极管的p +阳极置于底部，并且完全包围二极管。 n阱延伸到下拉FET的n +漏极区并接触。 n阱将p +区域与衬底隔离，允许p +区域连接到电源总线VSSO，从而消除了将金属电源总线VSSI布线到器件的I / O部分的要求。

    METHOD FOR INCORPORATING PATTERN DEPENDENT EFFECTS IN CIRCUIT SIMULATIONS
    14.
    发明申请
    METHOD FOR INCORPORATING PATTERN DEPENDENT EFFECTS IN CIRCUIT SIMULATIONS 有权
    在电路仿真中加入模式相关效应的方法

    公开(公告)号：US20110172983A1

    公开(公告)日：2011-07-14

    申请号：US13073291

    申请日：2011-03-28

    申请人： Jeffrey Watt

    发明人： Jeffrey Watt

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

    摘要翻译： 用于提供用于模拟的网表的方法，软件和装置，其包括由一个或多个模式相关效应确定的一个或多个参数。 本发明的一个具体实施例接收包括一个或多个MOSFET晶体管的电路的布局。 对于一个或多个MOSFET晶体管，使用接收的布局测量晶体管之间的间隔，并且确定模式相关参数。 该参数修改模拟中使用的门的长度。 在其他实施例中，可以使用其他模式相关效应来确定一个或多个参数的值。 这些参数可用于修改栅极长度，发射极尺寸，电阻器宽度或其他器件特性。

    Gate triggered ESD clamp
    16.
    发明授权
    Gate triggered ESD clamp 有权
    门触发ESD钳位

    公开(公告)号：US07098717B2

    公开(公告)日：2006-08-29

    申请号：US10877010

    申请日：2004-06-25

    申请人： Jeffrey Watt

    发明人： Jeffrey Watt

    IPC分类号： H03K5/08 ,  H03L5/00

    CPC分类号： H01L27/0274 ,  H01L27/0285

    摘要： The clamp circuit of the present invention comprises a low voltage, thin oxide MOS transistor and a trigger element comprising a timing element and at least one inverter. The source and drain of the MOS transistor are connected between a first node and a second node. The timing element comprises a capacitive element and a resistive element connected between the first and second nodes. The inverter is connected between a third node between the capacitive element and the resistive element and the gate of the MOS transistor. Advantageously, one or both of the capacitive element and the resistive element is also implemented in low voltage, thin oxide MOS transistors.

    摘要翻译： 本发明的钳位电路包括低电压，薄氧化物MOS晶体管和包括定时元件和至少一个反相器的触发元件。 MOS晶体管的源极和漏极连接在第一节点和第二节点之间。 定时元件包括电容元件和连接在第一和第二节点之间的电阻元件。 逆变器连接在电容元件和电阻元件之间的第三节点和MOS晶体管的栅极之间。 有利地，电容元件和电阻元件中的一个或两个也实现在低电压，薄氧化物MOS晶体管中。

    Techniques for trimming drive current in output drivers
    17.
    发明申请
    Techniques for trimming drive current in output drivers 有权
    调整输出驱动器驱动电流的技术

    公开(公告)号：US20060033532A1

    公开(公告)日：2006-02-16

    申请号：US10916908

    申请日：2004-08-11

    申请人： Jeffrey Watt

    发明人： Jeffrey Watt

    IPC分类号： H03K19/094

    CPC分类号： H03K19/00384 ,  H03K17/145 ,  H03K17/164

    摘要： Techniques are provided for trimming drive current in output drivers to compensate for process variations, model inaccuracies, and/or an off-target process. The actual output drive current is measured on the integrated circuit (IC) at wafer sort or during a final test. Based on the measured output drive current, the total transistor width that is required in the output driver to meet an I/O standard is calculated. A control block controls trimming transistors that are coupled in parallel with main output drive transistors. The control block adjusts the total width of the output drive transistors to bring the total width as close as possible to the desired width. Each I/O driver on a die can be adjusted individually based on its own drive current characteristics. All I/O drivers on a die can be adjusted by the same transistor width based on a single I/O measurement or on multiple I/O measurements.

    摘要翻译： 提供了用于修整输出驱动器中的驱动电流以补偿过程变化，模型不准确和/或偏离目标过程的技术。 实际输出驱动电流在晶圆分类或最终测试期间在集成电路（IC）上测量。 基于测量的输出驱动电流，计算输出驱动器满足I / O标准所需的总晶体管宽度。 控制块控制与主输出驱动晶体管并联耦合的微调晶体管。 控制块调节输出驱动晶体管的总宽度，使总宽度尽可能靠近所需的宽度。 芯片上的每个I / O驱动器可以根据其自身的驱动电流特性单独调整。 基于单个I / O测量或多个I / O测量，芯片上的所有I / O驱动器都可以通过相同的晶体管宽度进行调整。

    Method for incorporating pattern dependent effects in circuit simulations
    18.
    发明授权
    Method for incorporating pattern dependent effects in circuit simulations 有权
    将模式相关效应纳入电路仿真的方法

    公开(公告)号：US08434039B2

    公开(公告)日：2013-04-30

    申请号：US13073291

    申请日：2011-03-28

    申请人： Jeffrey Watt

    发明人： Jeffrey Watt

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5036

    摘要： Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

    摘要翻译： 用于提供用于模拟的网表的方法，软件和装置，其包括由一个或多个模式相关效应确定的一个或多个参数。 本发明的一个具体实施例接收包括一个或多个MOSFET晶体管的电路的布局。 对于一个或多个MOSFET晶体管，使用接收的布局测量晶体管之间的间隔，并且确定模式相关参数。 该参数修改模拟中使用的门的长度。 在其他实施例中，可以使用其他模式相关效应来确定一个或多个参数的值。 这些参数可用于修改栅极长度，发射极尺寸，电阻器宽度或其他器件特性。