公开(公告)号：US06629209B1

公开(公告)日：2003-09-30

申请号：US09437185

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

公开(公告)号：US06625701B1

公开(公告)日：2003-09-23

申请号：US09437183

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1214

CPC分类号： G06F12/0811 ,  G06F12/0815

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。 优选实施例提供具有高速缓存存储命令的指示符位，其特别地指示存储还是否用作锁定释放。

公开(公告)号：US06345342B1

公开(公告)日：2002-02-05

申请号：US09437177

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改的非请求（Mu）高速缓存状态，以指示保持在高速缓存行中的值已经被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用Mu状态。 读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US06321306B1

公开(公告)日：2001-11-20

申请号：US09437179

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1212

CPC分类号： G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用MU状态。 读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US06374333B1

公开(公告)日：2002-04-16

申请号：US09437176

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用MU状态。 读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US06345343B1

公开(公告)日：2002-02-05

申请号：US09437178

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用MU状态。 读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US06629214B1

公开(公告)日：2003-09-30

申请号：US09437186

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1300

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的缓存状态允许优化缓存状态转换序列。 特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器 一个修改。 通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。

公开(公告)号：US06345344B1

公开(公告)日：2002-02-05

申请号：US09437181

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in 5 a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改后的未经请求（Mu）高速缓存状态，以指示缓存行5中保存的值已经被修改（即当前与系统存储器不一致），但是被另一个处理单元修改 通过与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用Mu状态。 读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US07480772B2

公开(公告)日：2009-01-20

申请号：US11835984

申请日：2007-08-08

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US07197604B2

公开(公告)日：2007-03-27

申请号：US10965151

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。