公开(公告)号：US20060251207A1

公开(公告)日：2006-11-09

申请号：US11418169

申请日：2006-05-04

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: G11C19/00

CPC classification number: G11C19/287

Abstract: A barrel shifter receiving N symbols, arranged n2 distinct groups of n1 symbols, applying a circular shift to the N symbols. The barrel shifter comprises n2 first barrel shifters, each applying a first circular shift to one of the groups of n1 symbols; a rearrangement module receiving the N symbols provided by the first barrel shifters and providing N symbols arranged, in a determined manner, in n1 distinct groups of n2 symbols; n1 second barrel shifters, each applying a second circular shift to one of the distinct groups of n2 symbols; a control module providing, to each first barrel shifter, an identical signal bs_ctrl1 representing the first shift, and providing, to each second barrel shifter, an identical signal bs_ctrl2 representing the second shift; and a switching module switching at least two of the symbols of the N symbols.

Abstract translation: 一个桶形移位器，接收N个符号，排列n 2个不同的n个1个符号的组，对N个符号进行循环移位。 桶形移位器包括n个2个第一桶形移位器，每个第一桶形移位器向n个1个符号组中的一个施加第一循环移位; 接收由第一桶形移位器提供的N个符号并提供以确定的方式在n个2个符号的n个不同组中排列的N个符号的重排模块; n 1个第二桶形移位器，每个第二桶形移位器向n个符号的不同组中的一个施加第二循环移位; 控制模块向每个第一桶形移位器提供表示第一移位的相同信号bs_ctrl 1，并向每个第二桶形移位器提供表示第二移位的相同信号bs_ctrl 2; 以及切换模块切换N个符号的至少两个符号。

公开(公告)号：US20050281111A1

公开(公告)日：2005-12-22

申请号：US11158718

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: G11C7/00 ,  H03M13/11 ,  H04N7/16

CPC classification number: H03M13/6566 ,  H03M13/1137

Abstract: An LDPC decoder comprising processing units capable of receiving first messages and of providing second messages based on the first received messages; first and second single-port memories; and means for reading first words from the first and second memories, each first word containing first messages, providing first messages to the processing units based on the first read words, forming second words, each second word containing second messages provided by the processing units, and writing the second words into the first and second memories, said means being capable of reading a first (respectively second) word from the first memory and of simultaneously writing a second (respectively first) word into the second memory.

Abstract translation: 一种LDPC解码器，包括能够接收第一消息的处理单元和基于第一接收消息提供第二消息; 第一和第二单端口存储器; 以及用于从第一和第二存储器读取第一个单词的装置，每个第一个单词包含第一个消息，基于第一个读取的单词提供第一个消息给处理单元，形成第二个单词，每个第二个单词包含由处理单元提供的第二个消息， 并且将第二个字写入第一和第二存储器，所述装置能够从第一存储器读取第一（分别为第二）字，并且同时将第二（分别地）第一个字写入第二存储器。

公开(公告)号：US07966544B2

公开(公告)日：2011-06-21

申请号：US11737442

申请日：2007-04-19

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/2792

Abstract: An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N−K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.

Abstract translation: LDPC解码器的输入存储器加载与要解码的LDPC帧相对应的数据，并且包括N个LLR，其中K是信息LLR，N-K是奇偶校验LLR。 借助于串行/并行转换模块，至少一个流由第二类型的二进制字形成，每个二进制字对应于多个信息LLRS，并且至少一个流由第二类型的二进制字形成，每一个对应于 借助于包括二维先进先出环形缓冲器的行/列交织装置的多个奇偶校验LLR。 第一存储器访问是以页模式进行的，以便将第一类型的二进制字写入输入存储器的第一区，并且第二存储器访问以页模式进行，以便写入第二类的二进制字 到第二区。

公开(公告)号：US07810015B2

公开(公告)日：2010-10-05

申请号：US11563595

申请日：2006-11-27

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: G11C29/00

CPC classification number: H03M13/1105 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/1595 ,  H03M13/2906

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract translation: 一种级联信道解码方法，其中使用第一迭代块解码算法解码并且想要使用第二块解码算法进行解码的一组N1比特的比特在P比特的至少一个子集中并行发送到缓冲器， 临时存储。 解码方法包括：并行地接收属于发送到缓冲器的N1比特组的Q比特的至少一个子集，借助于第二解码算法检测错误，基于使用第一解码算法解码的比特，以及校正 存储在缓冲器中的位可以作为检测到的可能错误的函数。 检测错误和/或校正所存储的比特包括接收的Q位的每个子集的比特的并行处理。

公开(公告)号：US20090226115A1

公开(公告)日：2009-09-10

申请号：US12467886

申请日：2009-05-18

Applicant: Pascal Urard ,  Laurent Paumier ,  Yan Meroth

Inventor： Pascal Urard ,  Laurent Paumier ,  Yan Meroth

IPC: G06K9/32

CPC classification number: G06T1/60 ,  G09G5/391

Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract translation: 图像适配器通过连续地处理图块并且通过改变图像点的列和行的数量将输入图像转换成输出图像。 图像适配器包括串联连接的队列存储器，以便接收与输入图像的图块的点相关联的值。 用于计算加权平均的模块具有分别连接到其中一个存储器的输出的输入。 该模块产生在平行于列的方向上采样的值，并对应于与输入图像的点相关联的值。 连接到模块的输出的采样率转换器根据与行平行的方向确定的采样率产生与输出图像的点相关联的值。

公开(公告)号：US07551803B2

公开(公告)日：2009-06-23

申请号：US10959953

申请日：2004-10-06

Applicant: Pascal Urard ,  Laurent Paumier ,  Yan Meroth

Inventor： Pascal Urard ,  Laurent Paumier ,  Yan Meroth

IPC: G06K9/32

CPC classification number: G06T1/60 ,  G09G5/391

Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract translation: 图像适配器通过连续地处理图块并且通过改变图像点的列和行的数量将输入图像转换成输出图像。 图像适配器包括串联连接的队列存储器，以便接收与输入图像的图块的点相关联的值。 用于计算加权平均的模块具有分别连接到其中一个存储器的输出的输入。 该模块产生在平行于列的方向上采样的值，并对应于与输入图像的点相关联的值。 连接到模块的输出的采样率转换器根据与行平行的方向确定的采样率产生与输出图像的点相关联的值。

公开(公告)号：US07454693B2

公开(公告)日：2008-11-18

申请号：US11158718

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: G06F11/00

CPC classification number: H03M13/6566 ,  H03M13/1137

Abstract: An LDPC decoder having a determined number of processing units operating in parallel, storage circuitry capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each processing unit with a message of the first type or a message of the second type, and a message write unit capable of writing, into the storage circuitry, first words or second words. The message provision unit is capable of providing a message at a position in a word which depends on the word or the message write unit is capable of writing each message at a position in the word which depends on the word.

Abstract translation: 具有确定数量的处理单元并行操作的LDPC解码器，能够包含包含第一类型的消息的并置的第一个字的存储电路和包含第二类型的消息并置的第二个字，能够 向每个处理单元提供第一类型的消息或第二类型的消息;以及消息写入单元，其能够向存储电路写入第一字或第二字。 消息提供单元能够在单词中的位置处提供消息，该单词取决于单词或消息写入单元能够将每个消息写入取决于单词的单词中的位置。

公开(公告)号：US07308618B2

公开(公告)日：2007-12-11

申请号：US10880334

申请日：2004-06-29

Applicant: Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

IPC: G11C29/00

CPC classification number: H03M13/6502 ,  H03M13/27 ,  H03M13/2785 ,  H03M13/6566

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract translation: 交织器包括用于存储数据的两个随机存取存储器和连接到两个存储器的相应地址输入的寻址装置（100）。 寻址装置被设计成在时钟的每个时刻发送用于对两个存储器之一的读取访问的提示和用于对两个存储器中的另一个的写入访问的提示，使得在每个时刻，数据项 被写入或读取每个存储器。

公开(公告)号：US20070094565A1

公开(公告)日：2007-04-26

申请号：US11534476

申请日：2006-09-22

Applicant: Laurent Paumier ,  Pascal Urard ,  Martial Comminges

Inventor： Laurent Paumier ,  Pascal Urard ,  Martial Comminges

IPC: H03M13/00

CPC classification number: H03M13/6505 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6566

Abstract: A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing blocks of data from the first data stream and blocks of data from the second data stream, and a block decoding unit for processing, from the input memory, the blocks of data from the first and second data streams.

Abstract translation: 以例如SoC形式实现的系统包括用于产生要解码的第一数据流的第一解调器和用于产生待解码的第二数据流的第二解调器和块解码器。 块解码器包括用于存储来自第一数据流的数据块和来自第二数据流的数据块的输入存储器，以及块解码单元，用于从输入存储器处理来自第一和第二数据的数据块 流。

公开(公告)号：US20050283703A1

公开(公告)日：2005-12-22

申请号：US11158516

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: H03M13/00 ,  H03M13/11 ,  H04N7/16

CPC classification number: H03M13/1137 ,  H03M13/1105

Abstract: An LDPC decoder comprising a determined number of processing units operating in parallel, a storage means capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each processing unit with a message of the first type or a message of the second type, and a message write unit capable of writing, into the storage means, first words or second words. The message provision unit is capable of providing a message at a position in a word which depends on the word or the message write unit is capable of writing each message at a position in the word which depends on the word.

Abstract translation: 包括确定数量的并行操作的处理单元的LDPC解码器，能够包含包含第一类型的消息的并置的第一个字的存储装置和包含第二类型的消息的并置的第二字，能够 向每个处理单元提供第一类型的消息或第二类型的消息，以及能够将存储装置中的第一个字或第二个字写入的消息写入单元。 消息提供单元能够在单词中的位置处提供消息，该单词取决于单词或消息写入单元能够将每个消息写入取决于单词的单词中的位置。