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11.发明授权System, method and computer program product for providing quiesce filtering for shared memory 有权用于为共享存储器提供静默滤波的系统，方法和计算机程序产品公开(公告)号：US08458438B2
公开(公告)日：2013-06-04
申请号：US12037897
申请日：2008-02-26
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB1). It is determined that the shared-memory request can be filtered by the processor if there not any shared memory entries in the TLB1 and the donor zone is not equal to a current zone of the processor and the processor is not running in host mode. The shared-memory quiesce request is filtered in response to the determining.
摘要翻译： 一种用于为共享存储器提供静默滤波的系统，方法和计算机程序产品。 该方法包括在处理器处接收共享存储器静默请求。 请求包括捐助者区域。 处理器包括翻译后备缓冲区（TLB1）。 如果TLB1中没有任何共享存储器条目，并且供体区域不等于处理器的当前区域并且处理器未在主机模式下运行，则确定共享存储器请求可被处理器过滤。 响应于确定，对共享内存静默请求进行过滤。
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12.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES 有权用于提供多种状态机器的系统，方法和计算机程序产品公开(公告)号：US20090217269A1
公开(公告)日：2009-08-27
申请号：US12037734
申请日：2008-02-26
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译： 一种用于提供多个静默状态机的系统，方法和计算机程序产品。 该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。 该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。 处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。 因此，多个静默请求可能在系统中同时处于活动状态。
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公开(公告)号：US07020761B2
公开(公告)日：2006-03-28
申请号：US10436209
申请日：2003-05-12
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.
摘要翻译： 在某些情况下，计算环境的处理限制被过滤和阻止，使处理继续，尽管有限制。 响应于缓冲区错误，一个限制包括禁止地址转换的指示。 当计算环境的处理单元满足该限制时，它执行页面索引的比较，其指示地址转换是否可以继续。 如果地址转换可以继续，限制被忽略。 作为示例，处理单元包括处理器或可分页实体。
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14.发明申请SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING QUIESCE FILTERING FOR SHARED MEMORY 有权用于提供共享存储器的QUIESCE过滤的系统，方法和计算机程序产品公开(公告)号：US20090216995A1
公开(公告)日：2009-08-27
申请号：US12037897
申请日：2008-02-26
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB1). It is determined that the shared-memory request can be filtered by the processor if there not any shared memory entries in the TLB1 and the donor zone is not equal to a current zone of the processor and the processor is not running in host mode. The shared-memory quiesce request is filtered in response to the determining.
摘要翻译： 一种用于为共享存储器提供静默滤波的系统，方法和计算机程序产品。 该方法包括在处理器处接收共享存储器静默请求。 请求包括捐助者区域。 处理器包括翻译后备缓冲区（TLB1）。 如果TLB1中没有任何共享存储器条目，并且供体区域不等于处理器的当前区域并且处理器未在主机模式下运行，则确定共享存储器请求可被处理器过滤。 响应于确定，对共享内存静默请求进行过滤。
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公开(公告)号：US20130339627A1
公开(公告)日：2013-12-19
申请号：US13524063
申请日：2012-06-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.
摘要翻译： 提供了一种用于监视值而不重复存储访问的技术。 处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。 处理电路配置用于监视存储器位置的监视站。 存储器位置包括程序的状态描述符。 处理电路从存储器控制器接收到交叉无效请求。 交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。
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公开(公告)号：US08572624B2
公开(公告)日：2013-10-29
申请号：US12037734
申请日：2008-02-26
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译： 一种用于提供多个静默状态机的系统，方法和计算机程序产品。 该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。 该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。 处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。 因此，多个静默请求可能在系统中同时处于活动状态。
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公开(公告)号：US20080010407A1
公开(公告)日：2008-01-10
申请号：US11428858
申请日：2006-07-06
申请人： Ute Gaertner , Erwin F. Pfeffer , Bruce Wagar
发明人： Ute Gaertner , Erwin F. Pfeffer , Bruce Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set. Scrubbing can take place in the background, and can be suspended and resumed at any time so as to not impact request service times of the tables.
摘要翻译： 用于计算机阵列的缓冲索引（例如缓存）用于将父条目与子对象同步，并允许后台无效（即，如果数组的新请求进入，则在暂停请求满足后恢复无效）来暂停无效 子项。 同步的方法使用下级表中的（多个）条目与具有缓冲索引值的更高级别表中的单个条目的链接。 每次上级条目被替换或无效时，该索引值递增（从而与其对应的较低级别条目解除关联）。 维持多组索引值，因此当一个集合耗尽时，处理可以继续其他集合之一。 然后可以从新的（干净的）集合构建新的条目，然后可以擦除（无效）来自旧（脏）集合的索引值的所有相应的较低级别条目。 擦洗可以在后台进行，可以随时暂停和恢复，以免影响表的请求服务时间。
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公开(公告)号：US06766434B2
公开(公告)日：2004-07-20
申请号：US10126239
申请日：2002-04-19
申请人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).
摘要翻译： 本发明一般涉及诸如IBM ESA / 390或RS / 6000系统的共享存储器多处理器系统，更具体地涉及用于在多个CPU之间共享第二级转换后备缓冲器（TLB 2）的方法和系统（ 30a，... 30d），用于提高性能并减少缓冲虚拟到绝对地址转换结果所需的芯片面积。 本发明的TLB2组织包括专用于特定CPU的几个小阵列（32a，...，32d），提供与CPU之间共享的主阵列（21）的接口。 专用阵列32a，。 。 。 32d）需要满足架构约束并将多个CPU链接到常用的共享阵列（21）。
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公开(公告)号：US06418522B1
公开(公告)日：2002-07-09
申请号：US09501741
申请日：2000-02-11
申请人： Ute Gaertner , John MacDougall , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , John MacDougall , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F2212/681
摘要： The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.
摘要翻译： 由本发明构成的基本思想是提供一种有利地使用两个缓冲器，小的第一级TLB1和较大的第二级TLB2的翻译后备缓冲器（TLB）装置。 当所需的虚拟地址不包含在第一级TLB中时，第二级TLB将地址信息馈送到第一级TLB。 根据本发明，第二级TLB有利地包括两个n路组合关联子单元，其中一个较高级别单元覆盖一些较高级地址转换级别，而另一级单元覆盖一些较低级别的地址转换级别 级别翻译水平。 根据本发明，一些地址信息例如保持一些中间虚拟地址（MLVA）位，即8位，能够用作覆盖上位子单元的地址范围的索引地址。 因此，相同的信息用作下级子单元中的标签信息，并且在本文中用作任何查找操作中的快速参考，以便找到相关虚拟地址的绝对地址。 此外，常用的状态位，如; 例如有效位也用在两个TLB结构中。
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公开(公告)号：US5978957A
公开(公告)日：1999-11-02
申请号：US765003
申请日：1997-07-14
申请人： Wilhelm Haller , Klaus Getzlaff , Erwin Pfeffer , Ute Gaertner , Gunter Gerwig
发明人： Wilhelm Haller , Klaus Getzlaff , Erwin Pfeffer , Ute Gaertner , Gunter Gerwig
摘要： A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.
摘要翻译： PCT No.PCT / EP95 / 01456 Sec。 371日期1997年7月14日 102（e）日期1997年7月14日PCT提交1995年4月18日PCT公布。 公开号WO96 / 33455 日期1996年10月24日这里描述了将移动操作分离成可以在不同流水线分段中执行的部分班次的换档结构和方法。 在第一管道级中，读出操作数，并且通过将操作数或其部分放入耦合到移位单元的寄存器来实现至少一个部分移位。 在第二管段中的换档单元完成执行剩余部分换挡的换档操作，从而减少了总换档操作所需的时间。 基于移位量，在移位单元中导出控制串，以校正移位结果的输出以及为此进行奇偶校验。
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