公开(公告)号：US20240242759A1

公开(公告)日：2024-07-18

申请号：US18319513

申请日：2023-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: G11C11/4097 ,  G11C11/4067 ,  H10B12/10

CPC classification number: G11C11/4097 ,  G11C11/4067 ,  H10B12/10

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

公开(公告)号：US20240008249A1

公开(公告)日：2024-01-04

申请号：US18047662

申请日：2022-10-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A memory structure includes a substrate, a first gate structure, a second gate structure, a third gate structure, and channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along a first direction. The first gate structure, the second gate structure and the third gate structure are disposed on the substrate, and are separated from each other along the first direction and extend respectively along a second direction and a third direction. The first gate includes first, second and third island structures respectively extending along the third direction and separated from each other along the second direction. The third gate structure includes fourth, fifth and sixth island structures respectively extending along the third direction and separated from each other along the second direction.

公开(公告)号：US20230097416A1

公开(公告)日：2023-03-30

申请号：US17488128

申请日：2021-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Wei-Chen CHEN

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.

公开(公告)号：US20140361369A1

公开(公告)日：2014-12-11

申请号：US14163639

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting LUE ,  Wei-Chen CHEN

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

Abstract translation: 双模式晶体管结构包括半导体本体。 器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可操作为源极或漏极）和邻近沟道区的n型端子区域（可用作源极或漏极） 通道区域的第二侧。 栅极绝缘体设置在沟道区域上的半导体本体的表面上。 栅极设置在沟道区域上的栅极绝缘体上。 第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。 可选地，可以在通道区域下面包括后门。 可以使用偏置辅助栅极在单个器件中选择n沟道或p沟道模式。