公开(公告)号：US20160086665A1

公开(公告)日：2016-03-24

申请号：US14956022

申请日：2015-12-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan HSIAO ,  Hand-Ting LUE ,  Wei-Chen CHEN

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/11578 ,  H01L29/40117 ,  H01L29/7926

Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

Abstract translation: 3D存储器件包括改进的双栅极存储单元。 改进的双栅极存储单元具有通道体，其具有相对的第一和第二侧表面，第一和第二侧表面上的电荷存储结构以及覆盖第一和第二侧表面上的电荷存储结构的栅极结构。 通道体具有小于阈值通道体深度的第一和第二侧表面之间的深度，与构成该单元的有效通道长度大于阈值长度的栅极结构组合。 通道体深度与有效沟道长度的组合是相关联的，使得单元通道体可以完全耗尽，并且当存储单元在读取偏压下具有高阈值状态时，可以抑制亚阈值泄漏电流。

公开(公告)号：US20240407181A1

公开(公告)日：2024-12-05

申请号：US18457412

申请日：2023-08-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H10B99/00 ,  G11C5/06 ,  G11C11/39 ,  H01L29/74

Abstract: A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.

公开(公告)号：US20230240062A1

公开(公告)日：2023-07-27

申请号：US17746996

申请日：2022-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Ting FAN ,  Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/108 ,  H01L23/528

CPC classification number: H01L27/10802 ,  H01L23/5283

Abstract: A memory structure includes a substrate; a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along the first direction and respectively extending along the second direction and the third direction; channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction; dielectric films disposed between the first gate structure, the second gate structure, the third gate structure and the channel bodies; and a first side plug electrically connected to the substrate and the channel bodies. The first gate structure, the second gate structure and the third gate structure surround each of the dielectric films and each of the channel bodies, and the dielectric films do not include a charge storage structure.

公开(公告)号：US20220068922A1

公开(公告)日：2022-03-03

申请号：US17005550

申请日：2020-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/108 ,  H01L27/11556 ,  H01L27/11582 ,  G11C11/39 ,  G11C11/56

Abstract: A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.

公开(公告)号：US20140362644A1

公开(公告)日：2014-12-11

申请号：US14209962

申请日：2014-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting LUE ,  Wei-Chen CHEN

IPC: G11C16/12 ,  G11C16/14 ,  H01L27/115 ,  G11C16/26

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase.

Abstract translation: 存储器结构包括具有多栅极沟道区的半导体条，与沟道区的第一侧相邻的p型端子区和与沟道区的第二侧相邻的n型端子区。 多个字线布置成在沟道区域的交叉点处穿过半导体条。 位线耦合到半导体条的第一端，并且参考线耦合到半导体条的第二端。 电荷存储结构设置在多个字线中的字线和半导体条的沟道区之间，由此存储单元沿着位线和参考线之间的半导体条串联设置。 可以使用偏移未选择的字线来选择单个所选单元格中的n沟道或p沟道模式进行读取，编程或擦除。

公开(公告)号：US20240386976A1

公开(公告)日：2024-11-21

申请号：US18199308

申请日：2023-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH ,  Wei-Chen CHEN

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

公开(公告)号：US20220254799A1

公开(公告)日：2022-08-11

申请号：US17495826

申请日：2021-10-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Cheng-Lin SUNG ,  Wei-Chen CHEN

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device is provided. The semiconductor device includes a first vertical stack, a first vertical channel line, a first data storage structure, and a first gate dielectric structure. The first vertical stack includes a first conductive line and a second conductive line. The first vertical channel line vertically passes through the first conductive line and the second conductive line, and the first vertical channel line is a P-type channel. The first data storage structure is disposed between the first conductive line and the first vertical channel line. The first gate dielectric structure is disposed between the second conductive line and the first vertical channel line.

公开(公告)号：US20220231041A1

公开(公告)日：2022-07-21

申请号：US17149782

申请日：2021-01-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/10

Abstract: A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.

公开(公告)号：US20210193677A1

公开(公告)日：2021-06-24

申请号：US16923144

申请日：2020-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen CHEN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first location and a second location of the channel layer. The first location is opposite to the second location. The first location is surrounded by the memory structure, and the second location is exposed from the memory structure.

公开(公告)号：US20250078893A1

公开(公告)日：2025-03-06

申请号：US18240852

申请日：2023-08-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Teng-Hao YEH ,  Wei-Chen CHEN ,  Rachit DOBHAL ,  Zefu ZHAO ,  Chee-Wee LIU

IPC: G11C11/22 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.