公开(公告)号：US20230317166A1

公开(公告)日：2023-10-05

申请号：US17711073

申请日：2022-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Po-Hao TSENG ,  Feng-Min LEE

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.

公开(公告)号：US20230022008A1

公开(公告)日：2023-01-26

申请号：US17380056

申请日：2021-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Hsiu LEE ,  Po-Hao TSENG ,  Yu-Hsuan LIN

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device for data searching and a data searching method thereof are provided. The data searching method includes the following steps. A searching word is received and then divided into a plurality of sections. The sections are encoded as a plurality of encoded sections, so that the encoded sections may correspond to a plurality of memory blocks in a memory array. The encoded sections are directed into the memory blocks to perform data comparisons and obtaining a respective result of data comparison. Thereafter, addresses of bit lines which match the searching word are obtained according to respective result of data comparison for each of memory block.

公开(公告)号：US20200258573A1

公开(公告)日：2020-08-13

申请号：US16274301

申请日：2019-02-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuang-Hao CHIANG ,  Yu-Hsuan LIN

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A method for controlling accumulated resistance property of a ReRAM device, wherein the method includes steps as follows: A first programing pulse set is firstly applied to a ReRAM device for acquiring a reference accumulated resistance distribution. A second programing pulse set is then provided according to the reference accumulated resistance distribution, and the second programing pulse set is applied to the ReRAM device, to make the ReRAM device having a predetermined accumulated resistance distribution.

公开(公告)号：US20200027488A1

公开(公告)日：2020-01-23

申请号：US16154831

申请日：2018-10-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Chao-Hung WANG

IPC: G11C7/22 ,  G06F3/06

Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

公开(公告)号：US20250111874A1

公开(公告)日：2025-04-03

申请号：US18476411

申请日：2023-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Feng-Min LEE ,  Ming-Hsiu LEE ,  Yu-Yu LIN

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.

公开(公告)号：US20240386958A1

公开(公告)日：2024-11-21

申请号：US18785113

申请日：2024-07-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Yu-Hsuan LIN ,  Feng-Min LEE ,  Yung-Chun LI

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/26

Abstract: The application provides a content addressable memory (CAM) device and a method for searching and comparing data thereof. The CAM device comprises: a plurality of memory strings; and a sensing amplifier circuit coupled to the memory strings; wherein in data searching, a search data is compared with a storage data stored in the memory strings, the memory strings generate a plurality of string currents, the sensing amplifier circuit senses the string currents to generate a plurality of sensing results; based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.

公开(公告)号：US20240242767A1

公开(公告)日：2024-07-18

申请号：US18623116

申请日：2024-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Dai-Ying LEE ,  Ming-Hsiu LEE

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/40

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/40 ,  G11C2029/4002

Abstract: A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

公开(公告)号：US20230238061A1

公开(公告)日：2023-07-27

申请号：US17717192

申请日：2022-04-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Po-Hao TSENG

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

公开(公告)号：US20230034366A1

公开(公告)日：2023-02-02

申请号：US17388053

申请日：2021-07-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Po-Kai HSU ,  Ming-Liang WEI

IPC: G06N3/08

Abstract: The present invention discloses a memory and a training method for neutral network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neutral network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neutral network; and programming the memory according to the weights.

公开(公告)号：US20200227414A1

公开(公告)日：2020-07-16

申请号：US16249049

申请日：2019-01-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-Hung WANG ,  Yu-Hsuan LIN ,  Dai-Ying LEE

IPC: H01L27/105

Abstract: A semiconductor structure includes a memory array. The memory array has a plurality of memory units. The memory units include a first memory unit and a second memory unit. The first memory unit has a first resistance. The second memory unit has a second resistance. Both of the first resistance and the second resistance are in a range of 105Ω to 109Ω, and the second resistance is larger than the first resistance.