公开(公告)号：US20250022508A1

公开(公告)日：2025-01-16

申请号：US18903041

申请日：2024-10-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE ,  Ming-Hsiu LEE

IPC: G11C13/00 ,  G06F7/544

Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

公开(公告)号：US20240371453A1

公开(公告)日：2024-11-07

申请号：US18312630

申请日：2023-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G11C17/18 ,  G06F7/544 ,  G11C17/16

Abstract: A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.

公开(公告)号：US20240311620A1

公开(公告)日：2024-09-19

申请号：US18185751

申请日：2023-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G06N3/0464

CPC classification number: G06N3/0464

Abstract: A neural network computing method and a neural network computing device are provided. The neural network computing method includes the following steps. At least one chosen layer is decided. A plurality of front layers previous to the chosen layer are decided. A selected element is selected from a plurality of chosen elements in the chosen layer. A front computing data group related to the selected element is defined. The front computing data group is composed of only part of a plurality of front elements in the front layers. The selected element is computed according to the at least one front computing data group.

公开(公告)号：US20230273737A1

公开(公告)日：2023-08-31

申请号：US17680388

申请日：2022-02-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0673

Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.

公开(公告)号：US20190244662A1

公开(公告)日：2019-08-08

申请号：US15887166

申请日：2018-02-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Yu-Yu LIN

IPC: G11C13/00 ,  G06F7/544 ,  G11C16/04

CPC classification number: G11C11/54 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/2436

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

公开(公告)号：US20250095720A1

公开(公告)日：2025-03-20

申请号：US18469613

申请日：2023-09-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Yu-Yu LIN ,  Feng-Min LEE

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094

Abstract: A memory device includes a first memory cell performing a logic operation. The first memory cell includes first and second switches. The first switch writes a first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and a first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.

公开(公告)号：US20190220249A1

公开(公告)日：2019-07-18

申请号：US15873369

申请日：2018-01-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Yu-Yu LIN

IPC: G06F7/544 ,  H03K19/177

Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable threshold transistors in the array with thresholds corresponding to values of a weight factor Wmn for the corresponding cell. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

公开(公告)号：US20160351805A1

公开(公告)日：2016-12-01

申请号：US14723315

申请日：2015-05-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1633 ,  G11C13/0007 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.

Abstract translation: 本发明涉及基于金属氧化物的存储器件及其制造方法，更具体地涉及具有基于金属氧化物化合物的数据存储材料的存储器件，其中所述金属氧化物化合物通过偏置等离子体氧化工艺制造，该方法改善了存储元件与顶部 电极，用于在运行期间更均匀的电场，从而提高了器件的可靠性。

公开(公告)号：US20160218146A1

公开(公告)日：2016-07-28

申请号：US14746703

申请日：2015-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Yu-Yu LIN ,  Dai-Ying LEE

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.

Abstract translation: 本发明涉及基于金属氧化物的记忆装置及其制造方法。 并且更具体地涉及具有基于金属氧化物化合物的数据存储材料的存储器件，所述金属氧化物化合物在粗糙度调整过程包括在底部电极表面上形成存储元件之前包括底部电极表面的离子轰击步骤制造。 离子轰击改善了底部电极的平坦度，这有利于在操作期间实现更均匀的电场，这提高了器件的可靠性。

公开(公告)号：US20240219437A1

公开(公告)日：2024-07-04

申请号：US18147727

申请日：2022-12-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G01R19/257 ,  G01R19/00

CPC classification number: G01R19/257 ,  G01R19/0023

Abstract: An in-memory computing (IMC) memory device and an IMC method are provided. The IMC memory device includes: a plurality of memory cells, the memory cells forming a plurality of computing layers; and a plurality of computing layer connectors, the computing layer connectors connecting between the computing layers. A first computing layer input is inputted into a first computing layer of the computing layers. The first computing layer generates a first computing layer output. A first computing layer connector of the computing layer connectors converts the first computing layer output into a second computing layer input. The first computing layer connector inputs the second computing layer input into a second computing layer of the computing layers. The computing layer connectors are a plurality of inverters, a plurality of voltage-to-voltage converters or a plurality of current-to-voltage converters.