公开(公告)号：US20240365568A1

公开(公告)日：2024-10-31

申请号：US18307402

申请日：2023-04-26

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Methods, systems and apparatus for three-dimensional (3D) memory devices are provided. In one aspect, a semiconductor device includes: an array-side structure and a device-side structure. The array-side structure includes a memory array of memory cells and an array-side integrated circuit conductively coupled to the memory array. The device-side structure includes a device-side integrated circuit. The array-side structure and the device-side structure are integrated together with one or more connection pads therebetween. The array-side integrated circuit and the device-side integrated circuit are conductively coupled to each other through at least one of the one or more connection pads and configured to perform one or more operations on the memory array.

公开(公告)号：US20230290396A1

公开(公告)日：2023-09-14

申请号：US18319834

申请日：2023-05-18

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

公开(公告)号：US20230187359A1

公开(公告)日：2023-06-15

申请号：US18164626

申请日：2023-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76895 ,  H01L21/76805 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

公开(公告)号：US20220199134A1

公开(公告)日：2022-06-23

申请号：US17131437

申请日：2020-12-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

公开(公告)号：US20220173040A1

公开(公告)日：2022-06-02

申请号：US17109960

申请日：2020-12-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

公开(公告)号：US20210351196A1

公开(公告)日：2021-11-11

申请号：US16867063

申请日：2020-05-05

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/06 ,  G11C5/02

Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.