公开(公告)号：US20240284669A1

公开(公告)日：2024-08-22

申请号：US18169877

申请日：2023-02-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A memory device includes a substrate and a stack structure. A lower portion of the stack structure includes a first global selection line structure and a second global selection line structure. The first global selection line structure includes a first long strip, a first short strip and a first connection part connecting the first long strip and the first short strip. The first long strip and the second strip extend in a first direction, and the first connection part extends in a second direction different from the first direction. The first long strip passes through a staircase structure area from a first memory array area extending continuously to a second memory array area. The second global selection line structure is adjacent to the first global selection line structure and is divided into two portions separated from each other by the first connection part of the first global selection line structure.

公开(公告)号：US20250107082A1

公开(公告)日：2025-03-27

申请号：US18474615

申请日：2023-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Chih-Kai Yang ,  Shih-Chin Lee ,  Tzung-Ting Han

IPC: H10B43/27

Abstract: A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20250105213A1

公开(公告)日：2025-03-27

申请号：US18474231

申请日：2023-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Shao-En Chang ,  Tzung-Ting Han ,  Meng-Hsuan Weng ,  Chen-Yu Cheng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H10B80/00

Abstract: Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring.

公开(公告)号：US12256548B2

公开(公告)日：2025-03-18

申请号：US17748121

申请日：2022-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11578 ,  H01L27/11565 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.

公开(公告)号：US20240414921A1

公开(公告)日：2024-12-12

申请号：US18331805

申请日：2023-06-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

公开(公告)号：US12062615B2

公开(公告)日：2024-08-13

申请号：US18164626

申请日：2023-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

公开(公告)号：US11515319B2

公开(公告)日：2022-11-29

申请号：US16867063

申请日：2020-05-05

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/00 ,  H01L27/11556 ,  G11C5/02 ,  H01L27/06

Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

公开(公告)号：US20240355732A1

公开(公告)日：2024-10-24

申请号：US18302804

申请日：2023-04-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

公开(公告)号：US11727971B2

公开(公告)日：2023-08-15

申请号：US17131437

申请日：2020-12-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11582 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

公开(公告)号：US11610842B2

公开(公告)日：2023-03-21

申请号：US17109960

申请日：2020-12-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.