公开(公告)号：US20230238958A1

公开(公告)日：2023-07-27

申请号：US18065165

申请日：2022-12-13

Applicant: MEDIATEK INC.

Inventor： Bo-Ren LUNG ,  Jen-Hang YANG

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  H03K19/018507

Abstract: An integrated circuit device includes a reference voltage channel, a first cell and a second cell. The reference voltage channel is configured to provide a first reference voltage and a second reference voltage. The first cell is coupled to the reference voltage channel, and is configured to receive the first reference voltage and the second reference voltage. The second cell is coupled to the reference voltage channel, and is configured to receive the first reference voltage and the second reference voltage.

公开(公告)号：US20200065065A1

公开(公告)日：2020-02-27

申请号：US16111277

申请日：2018-08-24

Applicant: MEDIATEK INC.

Inventor： Ying-Chun WEI ,  Min-Hang HSIEH ,  Jen-Hang YANG

IPC: G06F7/503 ,  H03K19/017

Abstract: A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.

公开(公告)号：US20160011258A1

公开(公告)日：2016-01-14

申请号：US14330146

申请日：2014-07-14

Applicant: MediaTek Inc.

Inventor： Jen-Yi LIAO ,  Jen-Hang YANG

IPC: G01R31/3177

CPC classification number: G06F17/5072 ,  G01R31/318541 ,  G01R31/318583 ,  G06F2217/14

Abstract: A replacement method for scan cell of an integrated circuit (IC) is provided. A gate-level netlist of the IC is obtained. A place-and-route process is performed on the gate-level netlist to obtain a first netlist. A clock tree synthesis process is performed on the first netlist to obtain a second netlist. Static timing analysis is performed to analyze a plurality of first scan cells of the second netlist in normal mode and scan mode. The first scan cell is replaced with a second scan cell according to the static timing analysis that indicates the replaced first scan cell has a specific time margin in the scan mode. A first skew of the normal mode and a second skew of the scan mode are adjusted symmetrically in the first scan cell. The first skew and the second skew are adjusted asymmetrically in the second scan cell.

Abstract translation: 提供了集成电路（IC）的扫描单元的替代方法。 获得IC的门级网表。 在门级网表上执行布线处理以获得第一网表。 在第一网表上执行时钟树合成处理以获得第二网表。 执行静态时序分析以在正常模式和扫描模式下分析第二网表的多个第一扫描单元。 根据静态时序分析，用第二扫描单元替换第一个扫描单元，该静态时序分析指示被替换的第一扫描单元在扫描模式中具有特定的时间余量。 正常模式的第一偏移和扫描模式的第二偏移在第一扫描单元中对称地调整。 在第二扫描单元中第一偏斜和第二偏移被不对称地调整。