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11.发明授权公开(公告)号：US11223362B2
公开(公告)日：2022-01-11
申请号：US17242395
申请日：2021-04-28
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin , Tzu-Chan Chueh
Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.
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公开(公告)号：US09948265B2
公开(公告)日：2018-04-17
申请号：US15050436
申请日：2016-02-22
Applicant: MEDIATEK INC.
Inventor： Kun-Yin Wang , Wei-Hao Chiu , Ang-Sheng Lin
CPC classification number: H03H7/0115 , H01F17/0006 , H01F2017/0073 , H03H5/12
Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.
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公开(公告)号：US20160261273A1
公开(公告)日：2016-09-08
申请号：US14636190
申请日：2015-03-03
Applicant: Mediatek Inc.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin , Kun-Yin Wang
IPC: H03K21/02
CPC classification number: H03K23/667 , H03K21/38
Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.
Abstract translation: 一种分频装置包括：多个锁存装置，被配置为根据输入时钟信号和第一复位信号有选择地产生具有与第一振荡频率不同的第一振荡频率或第二振荡频率的输出信号; 以及控制装置，其布置成至少根据编程输入信号产生所述第一复位信号; 其中所述第一复位信号被布置成复位所述多个锁存装置中的第一锁定装置，以使所述多个锁存装置产生具有所述第二振荡频率的输出信号。
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公开(公告)号：US08831549B2
公开(公告)日：2014-09-09
申请号：US13795080
申请日：2013-03-12
Applicant: MEDIATEK Inc.
Inventor： Ang-Sheng Lin , Wei-Hao Chiu
CPC classification number: H04B1/16 , H04B1/30 , H04B2001/305
Abstract: A receiver circuit, e.g., a low-IF receiver, including two mixing paths. The two mixing paths scale an input signal respectively by two mixing gains and shift phase of the input signal respectively by two mixing phase offsets to provide two mixed signals. The two mixing gains and the two mixing phase offsets are arranged to produce an amplitude adjustment between amplitudes of the two mixed signals and a phase difference of 90 degrees plus a phase adjustment between phases of the two mixed signals. With the amplitude adjustment and/or the phase adjustment properly tuned to nonzero value(s) in association with band-pass response of the receiver circuit, image rejection can be achieved and optimized. Associated method is also disclosed.
Abstract translation: 接收机电路，例如低中频接收机，包括两个混合路径。 两个混合路径分别通过两个混合增益和输入信号的移相相分别通过两个混合相位偏移量化输入信号以提供两个混合信号。 两个混合增益和两个混合相位偏移被布置成在两个混合信号的振幅之间产生幅度调整，并且在两个混合信号的相位之间产生90度的相位差和相位调整。 通过与接收器电路的带通响应相关联的幅度调整和/或相位调整被适当地调谐到非零值，可以实现和优化镜像抑制。 还公开了相关方法。
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公开(公告)号：US20140080437A1
公开(公告)日：2014-03-20
申请号：US13795080
申请日：2013-03-12
Applicant: MEDIATEK INC.
Inventor： Ang-Sheng Lin , Wei-Hao Chiu
IPC: H04B1/16
CPC classification number: H04B1/16 , H04B1/30 , H04B2001/305
Abstract: A receiver circuit, e.g., a low-IF receiver, including two mixing paths. The two mixing paths scale an input signal respectively by two mixing gains and shift phase of the input signal respectively by two mixing phase offsets to provide two mixed signals. The two mixing gains and the two mixing phase offsets are arranged to produce an amplitude adjustment between amplitudes of the two mixed signals and a phase difference of 90 degrees plus a phase adjustment between phases of the two mixed signals. With the amplitude adjustment and/or the phase adjustment properly tuned to nonzero value(s) in association with band-pass response of the receiver circuit, image rejection can be achieved and optimized. Associated method is also disclosed.
Abstract translation: 接收机电路，例如低中频接收机，包括两个混合路径。 两个混合路径分别通过两个混合增益和输入信号的移相相分别通过两个混合相位偏移量化输入信号以提供两个混合信号。 两个混合增益和两个混合相位偏移被布置成在两个混合信号的振幅之间产生幅度调整，并且在两个混合信号的相位之间产生90度的相位差和相位调整。 通过与接收器电路的带通响应相关联的幅度调整和/或相位调整被适当地调谐到非零值，可以实现和优化镜像抑制。 还公开了相关方法。
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Patent Agency Ranking
公开(公告)号：US10778145B2
公开(公告)日：2020-09-15
申请号：US16681771
申请日：2019-11-12
Applicant: MEDIATEK INC.
Inventor： Yu-Li Hsueh , Po-Chun Huang , Ang-Sheng Lin , Wei-Hao Chiu
IPC: H03B5/12
Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
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公开(公告)号：US09473147B2
公开(公告)日：2016-10-18
申请号：US14636190
申请日：2015-03-03
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin , Kun-Yin Wang
CPC classification number: H03K23/667 , H03K21/38
Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.
Abstract translation: 一种分频装置包括：多个锁存装置，被配置为根据输入时钟信号和第一复位信号有选择地产生具有与第一振荡频率不同的第一振荡频率或第二振荡频率的输出信号; 以及控制装置，其布置成至少根据编程输入信号产生所述第一复位信号; 其中所述第一复位信号被布置成复位所述多个锁存装置中的第一锁定装置，以使所述多个锁存装置产生具有所述第二振荡频率的输出信号。
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公开(公告)号：US09397557B2
公开(公告)日：2016-07-19
申请号：US14278207
申请日：2014-05-15
Applicant: MediaTek Inc.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin
CPC classification number: H02M3/07 , H02M1/00 , H02M2001/0025 , H02M2001/0083 , H03L7/0895 , H03L7/0896
Abstract: A charge pump at least includes a current source, a first switch, a second switch, a level-shift circuit, and a capacitor. The first switch is coupled between the current source and an internal node. The capacitor is coupled between the internal node and the level-shift circuit. The second switch is coupled between the internal node and an output node. The first switch performs a closing-and-opening operation and the level-shift circuit performs a level-shift operation while the second switch is kept open and the internal node is isolated from the output node. The operating range of the charge pump is effectively widened by using the proposed design.
Abstract translation: 电荷泵至少包括电流源，第一开关，第二开关，电平移位电路和电容器。 第一个开关耦合在电流源和内部节点之间。 电容器耦合在内部节点和电平移位电路之间。 第二个开关耦合在内部节点和输出节点之间。 第一开关执行关闭和打开操作，并且电平移位电路在第二开关保持打开并且内部节点与输出节点隔离的同时执行电平移位操作。 通过使用提出的设计，电荷泵的工作范围得到有效的扩大。
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19.发明授权Current generating circuit, current generating method, charge pumping circuit and charge pumping method 有权电流产生电路，电流产生方法，电荷泵浦电路和电荷泵送方法公开(公告)号：US09331569B1
公开(公告)日：2016-05-03
申请号：US14596238
申请日：2015-01-14
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin
CPC classification number: H02M3/07
Abstract: A current generating circuit, which comprises: a first capacitor, comprising a first terminal and a second terminal; a second capacitor, comprising a first terminal and a second terminal; a first charge adjusting path, arranged for adjusting charges of the first capacitor according to a first charge adjusting voltage; a second charge adjusting path, arranged for adjusting charges of the second capacitor according to the first charge adjusting voltage; and a current generating path, coupled to the first capacitor and the second capacitor, arranged for generating a target current based on a difference between a first voltage provided by the first capacitor and a second voltage provided by the second capacitor.
Abstract translation: 一种电流产生电路，包括：第一电容器，包括第一端子和第二端子; 第二电容器，包括第一端子和第二端子; 第一电荷调整路径，被布置为根据第一电荷调节电压来调节所述第一电容器的电荷; 第二电荷调整路径，被布置为根据第一电荷调节电压调整第二电容器的电荷; 以及电流产生路径，耦合到所述第一电容器和所述第二电容器，用于基于由所述第一电容器提供的第一电压和由所述第二电容器提供的第二电压之间的差产生目标电流。
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公开(公告)号：US20160048145A1
公开(公告)日：2016-02-18
申请号：US14459305
申请日：2014-08-13
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Kun-Yin Wang , Ang-Sheng Lin
CPC classification number: G05F1/46 , H04B1/0475 , H04L27/20
Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.
Abstract translation: 一种电压发生电路，包括：输出电流产生电路，根据输出电压控制信号产生输出电流，使得在输出端产生输出电压; 比较装置，包括接收参考电压的第一输入端子，接收与输出电压相关的反馈电压的第二输入端子以及根据参考电压和反馈电压输出输出电压控制信号的输出端子; 一个可调降压电路，包括耦合到第二输入端的第一端和耦合到输出端的第二端; 以及电流源，用于向可调压降电路的第一端产生预定电流，从而在可调压降电路的第一端产生反馈电压。 预定电流流过可调压降电路到输出端。
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