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1.发明公开公开(公告)号：US20230317598A1
公开(公告)日：2023-10-05
申请号：US18119805
申请日：2023-03-09
Applicant: MEDIATEK INC.
Inventor： Ang-Sheng Lin , Yen-Liang Yeh , Hao-Wei Huang
IPC: H01L23/522 , H01L23/66
CPC classification number: H01L23/5227 , H01L23/66 , H01L28/10 , H01L2223/6672
Abstract: A semiconductor device includes a metal layer, a ground plane formed on the metal layer, a first inductor formed on the metal layer, and a first isolation region formed on the metal layer and arranged to separate the first inductor from the ground plane. The first isolation region includes a first main area surrounding the first inductor, and at least one first slot extended from the first main area.
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公开(公告)号：US20210320622A1
公开(公告)日：2021-10-14
申请号：US17114410
申请日：2020-12-07
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Ang-Sheng Lin , Wei-Hao Chiu
Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.
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公开(公告)号：US20200212843A1
公开(公告)日：2020-07-02
申请号：US16681771
申请日：2019-11-12
Applicant: MEDIATEK INC.
Inventor： Yu-Li Hsueh , Po-Chun Huang , Ang-Sheng Lin , Wei-Hao Chiu
IPC: H03B5/12
Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
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公开(公告)号：US10018970B2
公开(公告)日：2018-07-10
申请号：US15244132
申请日：2016-08-23
Applicant: MEDIATEK Inc.
Inventor： Yun-Chen Chuang , Ang-Sheng Lin
CPC classification number: G04F10/005 , H03L7/085 , H03L7/16 , H03L2207/50
Abstract: A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.
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公开(公告)号：US20170111009A1
公开(公告)日：2017-04-20
申请号：US15262003
申请日：2016-09-11
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Tzu-Chan Chueh , Ang-Sheng Lin
IPC: H03B5/12
Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
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Patent Agency Ranking
公开(公告)号：US09298199B2
公开(公告)日：2016-03-29
申请号：US14459305
申请日：2014-08-13
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Kun-Yin Wang , Ang-Sheng Lin
CPC classification number: G05F1/46 , H04B1/0475 , H04L27/20
Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.
Abstract translation: 一种电压发生电路，包括：输出电流产生电路，根据输出电压控制信号产生输出电流，使得在输出端产生输出电压; 比较装置，包括接收参考电压的第一输入端子，接收与输出电压相关的反馈电压的第二输入端子以及根据参考电压和反馈电压输出输出电压控制信号的输出端子; 一个可调降压电路，包括耦合到第二输入端的第一端和耦合到输出端的第二端; 以及电流源，用于向可调压降电路的第一端产生预定电流，从而在可调压降电路的第一端产生反馈电压。 预定电流流过可调压降电路到输出端。
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公开(公告)号：US11340641B2
公开(公告)日：2022-05-24
申请号：US16590391
申请日：2019-10-02
Applicant: MEDIATEK INC.
Inventor： Chun-Wei Chang , Song-Yu Yang , Ang-Sheng Lin
Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.
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公开(公告)号：US20220149849A1
公开(公告)日：2022-05-12
申请号：US17488339
申请日：2021-09-29
Applicant: MEDIATEK INC.
Inventor： Ang-Sheng Lin , Chun-Wei Chang , Tzu-Chan Chueh
Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
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公开(公告)号：US11152891B1
公开(公告)日：2021-10-19
申请号：US17114410
申请日：2020-12-07
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Ang-Sheng Lin , Wei-Hao Chiu
Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.
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公开(公告)号：US10425038B2
公开(公告)日：2019-09-24
申请号：US15262003
申请日：2016-09-11
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Tzu-Chan Chueh , Ang-Sheng Lin
Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
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